-
1
-
-
84863049778
-
Scaling feasibility study of planar thin floating gate (FG) NAND Flash devices and size effect challenges beyond 20 nm
-
H.-T. Lue, Y.-H. Hsiao, K.-Y. Hsieh, S.-Y. Wang, T. Yang, K.-C. Chen, and C.-Y. Lu, "Scaling feasibility study of planar thin floating gate (FG) NAND Flash devices and size effect challenges beyond 20 nm," in IEDM Tech. Dig., 2011, pp. 203-206.
-
(2011)
IEDM Tech. Dig
, pp. 203-206
-
-
Lue, H.-T.1
Hsiao, Y.-H.2
Hsieh, K.-Y.3
Wang, S.-Y.4
Yang, T.5
Chen, K.-C.6
Lu, C.-Y.7
-
2
-
-
17644422802
-
Toward a universal memory
-
DOI 10.1126/science.1110549
-
J. Akerman, "Applied physics: Toward a universal memory," Science, vol. 308, no. 5721, pp. 508-510, Apr. 22, 2005. (Pubitemid 40570573)
-
(2005)
Science
, vol.308
, Issue.5721
, pp. 508-510
-
-
Akerman, J.1
-
3
-
-
84866560375
-
Enhancement of data retention and write current scaling for sub-20 nm STT-MRAMby utilizing dual interfaces for perpendicular magnetic anisotropy
-
J.-H. Park, Y. Kim, W. C. Lim, J. H. Kim, S. H. Park, J. H. Kim, W. Kim, K. W. Kim, J. H. Jeong, K. S. Kim, H. Kim, Y. J. Lee, S. C. Oh, J. E. Lee, S. O. Park, S. Watts, D. Apalkov, V. Nikitin, M. Krounbi, S. Jeong, S. Choi, H. K. Kang, and C. Chung, "Enhancement of data retention and write current scaling for sub-20 nm STT-MRAMby utilizing dual interfaces for perpendicular magnetic anisotropy," in VLSI Symp. Tech. Dig., 2012, pp. 57-58.
-
(2012)
VLSI Symp. Tech. Dig
, pp. 57-58
-
-
Park, J.-H.1
Kim, Y.2
Lim, W.C.3
Kim, J.H.4
Park, S.H.5
Kim, J.H.6
Kim, W.7
Kim, K.W.8
Jeong, J.H.9
Kim, K.S.10
Kim, H.11
Lee, Y.J.12
Oh, S.C.13
Lee, J.E.14
Park, S.O.15
Watts, S.16
Apalkov, D.17
Nikitin, V.18
Krounbi, M.19
Jeong, S.20
Choi, S.21
Kang, H.K.22
Chung, C.23
more..
-
4
-
-
57149128202
-
Magnetoresistive random access memory: The path to competitiveness and scalability
-
Nov
-
J.-G. Zhu, "Magnetoresistive random access memory: The path to competitiveness and scalability," Proc. IEEE, vol. 96, no. 11, pp. 1786-1798, Nov. 2008.
-
(2008)
Proc. IEEE
, vol.96
, Issue.11
, pp. 1786-1798
-
-
Zhu, J.-G.1
-
5
-
-
4544362883
-
Scaling analysis of phase-change memory technology
-
A. Pirovano, A. L. Lacaita, A. Benvenuti, F. Pellizzer, S. Hudgens, and R. Bez, "Scaling analysis of phase-change memory technology," in IEDM Tech. Dig., 2003, pp. 29. 6. 1-29. 6. 4.
-
(2003)
IEDM Tech. Dig
, pp. 2961-2964
-
-
Pirovano, A.1
Lacaita, A.L.2
Benvenuti, A.3
Pellizzer, F.4
Hudgens, S.5
Bez, R.6
-
6
-
-
78650005927
-
Phase change memory
-
Dec.
-
H.-S. P. Wong, S. Raoux, S. Kim, J. Liang, J. P. Reifenberg, B. Rajendran, M. Asheghi, and K. E. Goodson, "Phase change memory," Proc. IEEE, vol. 98, no. 12, pp. 2201-2227, Dec. 2010.
-
(2010)
Proc. IEEE
, vol.98
, Issue.12
, pp. 2201-2227
-
-
Wong, H.-S.P.1
Raoux, S.2
Kim, S.3
Liang, J.4
Reifenberg, J.P.5
Rajendran, B.6
Asheghi, M.7
Goodson, K.E.8
-
7
-
-
84866561249
-
Scalable 3-D vertical chain-cell-type phase-change memory with 4F2 poly-Si diodes
-
M. Kinoshita, Y. Sasago, H. Minemura, Y. Anzai, M. Tai, Y. Fujisaki, S. Kusaba, T. Morimoto, T. Takahama, T. Mine, A. Shima, Y. Yonamoto, and T. Kobayashi, "Scalable 3-D vertical chain-cell-type phase-change memory with 4F2 poly-Si diodes," in Proc. VLSI Symp. Technol., 2012, pp. 35-36.
-
(2012)
Proc. VLSI Symp. Technol
, pp. 35-36
-
-
Kinoshita, M.1
Sasago, Y.2
Minemura, H.3
Anzai, Y.4
Tai, M.5
Fujisaki, Y.6
Kusaba, S.7
Morimoto, T.8
Takahama, T.9
Mine, T.10
Shima, A.11
Yonamoto, Y.12
Kobayashi, T.13
-
8
-
-
84872874183
-
High-density charge storage on molecular thin films-Candidate materials for high storage capacity memory cells
-
S. Paydavosi, K. Aidala, P. R. Brown, P. Hashemi, T. P. Osedach, J. L. Hoyt, and V. Bulovic, "High-density charge storage on molecular thin films-Candidate materials for high storage capacity memory cells," in IEDM Tech. Dig., 2011, pp. 24. 4. 1-24. 4. 4.
-
(2011)
IEDM Tech. Dig
, pp. 2441-2444
-
-
Paydavosi, S.1
Aidala, K.2
Brown, P.R.3
Hashemi, P.4
Osedach, T.P.5
Hoyt, J.L.6
Bulovic, V.7
-
9
-
-
84872866440
-
A low-voltage 1 Mb FRAM in 130 μm CMOS featuring time-to-digital sensing for expanded operating margin
-
Jan.
-
M. Qazi, M. Clinton, S. Bartling, and A. P. Chandrakasan, "A low-voltage 1 Mb FRAM in 130 μm CMOS featuring time-to-digital sensing for expanded operating margin," IEEE J. Solid-State Circuits, vol. 47, no. 1, pp. 141-150, Jan. 2012.
-
(2012)
IEEE J. Solid-State Circuits
, vol.47
, Issue.1
, pp. 141-150
-
-
Qazi, M.1
Clinton, M.2
Bartling, S.3
Chandrakasan, A.P.4
-
10
-
-
35748974883
-
Nanoionics-based resistive switching memories
-
DOI 10.1038/nmat2023, PII NMAT2023
-
R. Waser and M. Aono, "Nanoionics-based resistive switching memories," Nat. Mater., vol. 6, no. 11, pp. 833-840, Nov. 2007. (Pubitemid 350064191)
-
(2007)
Nature Materials
, vol.6
, Issue.11
, pp. 833-840
-
-
Waser, R.1
Aono, M.2
-
11
-
-
51949093158
-
A unified physical model of switching behavior in oxide-based RRAM
-
N. Xu, B. Gao, L. F. Liu, B. Sun, X. Y. Liu, R. Q. Han, J. F. Kang, and B. Yu, "A unified physical model of switching behavior in oxide-based RRAM," in Proc. VLSI Symp. Technol., 2008, pp. 100-101.
-
(2008)
Proc. VLSI Symp. Technol
, pp. 100-101
-
-
Xu, N.1
Gao, B.2
Liu, L.F.3
Sun, B.4
Liu, X.Y.5
Han, R.Q.6
Kang, J.F.7
Yu, B.8
-
12
-
-
84861125089
-
Metal-oxide RRAM
-
Jun.
-
H.-S. P. Wong, H.-Y. Lee, S. Yu, Y.-S. Chen, Y. Wu, P.-S. Chen, B. Lee, F. T. Chen, and M.-J. Tsai, "Metal-oxide RRAM," Proc. IEEE, vol. 100, no. 6, pp. 1951-1970, Jun. 2012.
-
(2012)
Proc. IEEE
, vol.100
, Issue.6
, pp. 1951-1970
-
-
Wong, H.-S.P.1
Lee, H.-Y.2
Yu, S.3
Chen, Y.-S.4
Wu, Y.5
Chen, P.-S.6
Lee, B.7
Chen, F.T.8
Tsai, M.-J.9
-
13
-
-
84859218369
-
On the switching parameter variation of metal-oxide RRAM-Part I: Physical modeling and simulation methodology
-
Apr.
-
X. Guan, S. Yu, and H.-S. P. Wong, "On the switching parameter variation of metal-oxide RRAM-Part I: Physical modeling and simulation methodology," IEEE Trans. Electron Devices, vol. 59, no. 4, pp. 1172-1182, Apr. 2012.
-
(2012)
IEEE Trans. Electron Devices
, vol.59
, Issue.4
, pp. 1172-1182
-
-
Guan, X.1
Yu, S.2
Wong, H.-S.P.3
-
14
-
-
84859216579
-
On the switching parameter variation of metal oxide RRAM-Part II: Model corroboration and device design strategy
-
Apr.
-
S. Yu, X. Guan, and H.-S. P. Wong, "On the switching parameter variation of metal oxide RRAM-Part II: Model corroboration and device design strategy," IEEE Trans. Electron Devices, vol. 59, no. 4, pp. 1183-1188, Apr. 2012.
-
(2012)
IEEE Trans. Electron Devices
, vol.59
, Issue.4
, pp. 1183-1188
-
-
Yu, S.1
Guan, X.2
Wong, H.-S.P.3
-
15
-
-
84863068618
-
Oxide-based RRAM: Unified microscopic principle for both unipolar and bipolar switching
-
B. Gao, J. F. Kang, Y. S. Chen, F. F. Zhang, B. Chen, P. Huang, L. F. Liu, X. Y. Liu, Y. Y. Wang, X. A. Tran, Z. R. Wang, H. Y. Yu, and A. Chin, "Oxide-based RRAM: Unified microscopic principle for both unipolar and bipolar switching," in IEDM Tech. Dig., 2011, pp. 17. 4. 1-17. 4. 4.
-
(2011)
IEDM Tech. Dig
, pp. 1741-1744
-
-
Gao, B.1
Kang, J.F.2
Chen, Y.S.3
Zhang, F.F.4
Chen, B.5
Huang, P.6
Liu, L.F.7
Liu, X.Y.8
Wang, Y.Y.9
Tran, X.A.10
Wang, Z.R.11
Yu, H.Y.12
Chin, A.13
-
16
-
-
84866125980
-
The 3D stacking bipolar RRAM for high density
-
Sep.
-
Y. Chen, H. Li, W. Zhang, and R. Pino, "The 3D stacking bipolar RRAM for high density," IEEE Trans. Nanotechnol., vol. 11, no. 5, pp. 948-956, Sep. 2012.
-
(2012)
IEEE Trans. Nanotechnol
, vol.11
, Issue.5
, pp. 948-956
-
-
Chen, Y.1
Li, H.2
Zhang, W.3
Pino, R.4
-
17
-
-
82955188020
-
Nanowire-based RRAM crossbar memory with metallic core-oxide shell nanostructure
-
C. Cagli, F. Nardi, D. Ielmini, B. Harteneck, Z. Tan, and Y. Zhang, "Nanowire-based RRAM crossbar memory with metallic core-oxide shell nanostructure," Proc. ESSDERC, pp. 103-106, 2011.
-
(2011)
Proc. ESSDERC
, pp. 103-106
-
-
Cagli, C.1
Nardi, F.2
Ielmini, D.3
Harteneck, B.4
Tan, Z.5
Zhang, Y.6
-
18
-
-
55349143194
-
Nano-crossbar arrays for nonvolatile resistive RAM (RRAM) applications
-
C. Nauenheim, C. Kugeler, A. Rudiger, R. Waser, A. Flocke, and T. G. Noll, "Nano-crossbar arrays for nonvolatile resistive RAM (RRAM) applications," Proc. 8th IEEE Conf. NANO, pp. 464-467, 2008.
-
(2008)
Proc. 8th IEEE Conf. NANO
, pp. 464-467
-
-
Nauenheim, C.1
Kugeler, C.2
Rudiger, A.3
Waser, R.4
Flocke, A.5
Noll, T.G.6
-
19
-
-
80052662353
-
High performance unipolar AlOy/HfOx/Ni based RRAM compatible with Si diodes for 3D application
-
X. A. Tran, B. Gao, J. F. Kang, L. Wu, Z. R. Wang, Z. Fang, K. L. Pey, Y. C. Yeo, A. Y. Du, B. Y. Nguyen, M. F. Li, and H. Y. Yu, "High performance unipolar AlOy/HfOx/Ni based RRAM compatible with Si diodes for 3D application," in Proc. VLSI Symp. Technol., 2011, pp. 44-45.
-
(2011)
Proc. VLSI Symp. Technol
, pp. 44-45
-
-
Tran, X.A.1
Gao, B.2
Kang, J.F.3
Wu, L.4
Wang, Z.R.5
Fang, Z.6
Pey, K.L.7
Yeo, Y.C.8
Du, A.Y.9
Nguyen, B.Y.10
Li, M.F.11
Yu, H.Y.12
-
20
-
-
84863052217
-
One selector-one resistor (1S1R) crossbar array for high-density flexible memory applications
-
J.-J. Huang, Y.-M. Tseng, W.-C. Luo, C.-W. Hsu, and T.-H. Hou, "One selector-one resistor (1S1R) crossbar array for high-density flexible memory applications," IEDM Tech. Dig., pp. 31. 7. 1-31. 7. 4, 2011.
-
(2011)
IEDM Tech. Dig
, pp. 3171-3174
-
-
Huang, J.-J.1
Tseng, Y.-M.2
Luo, W.-C.3
Hsu, C.-W.4
Hou, T.-H.5
-
21
-
-
79951830138
-
Threedimensional 4F2 ReRAM cell with CMOS logic compatible process
-
C.-H. Wang, Y.-H. Tsai, K.-C. Lin, M.-F. Chang, Y.-C. King, C.-J. Lin, S.-S. Sheu, Y.-S. Chen, H.-Y. Lee, F. T. Chen, and M.-J. Tsai, "Threedimensional 4F2 ReRAM cell with CMOS logic compatible process," in IEDM Tech. Dig., 2010, pp. 29. 6. 1-29. 6. 4.
-
(2010)
IEDM Tech. Dig
, pp. 2961-2964
-
-
Wang, C.-H.1
Tsai, Y.-H.2
Lin, K.-C.3
Chang, M.-F.4
King, Y.-C.5
Lin, C.-J.6
Sheu, S.-S.7
Chen, Y.-S.8
Lee, H.-Y.9
Chen, F.T.10
Tsai, M.-J.11
-
22
-
-
64549101091
-
Stack friendly all-oxide 3D RRAM using GaInZnO peripheral TFT realized over glass substrates
-
M.-J. Lee, C. B. Lee, S. Kim, H. Yin, J. Park, S. E. Ahn, B. S. Kang, K. H. Kim, G. Stefanovich, I. Song, S. W. Kim, J. H. Lee, S. J. Chung, Y. H. Kim, C. S. Lee, J. B. Park, I. G. Baek, C. J. Kim, and Y. Park, "Stack friendly all-oxide 3D RRAM using GaInZnO peripheral TFT realized over glass substrates," in IEDM Tech. Dig., 2008, pp. 1-4.
-
(2008)
IEDM Tech. Dig
, pp. 1-4
-
-
Lee, M.-J.1
Lee, C.B.2
Kim, S.3
Yin, H.4
Park, J.5
Ahn, S.E.6
Kang, B.S.7
Kim, K.H.8
Stefanovich, G.9
Song, I.10
Kim, S.W.11
Lee, J.H.12
Chung, S.J.13
Kim, Y.H.14
Lee, C.S.15
Park, J.B.16
Baek, I.G.17
Kim, C.J.18
Park, Y.19
-
23
-
-
84857007298
-
Complementary switching in metal oxides: Toward diode-less crossbar RRAMs
-
F. Nardi, S. Balatti, S. Larentis, and D. Ielmini, "Complementary switching in metal oxides: Toward diode-less crossbar RRAMs," in IEDM Tech. Dig., 2011, pp. 31. 1. 1-31. 1. 4.
-
(2011)
IEDM Tech. Dig
, pp. 3111-3114
-
-
Nardi, F.1
Balatti, S.2
Larentis, S.3
Ielmini, D.4
-
24
-
-
77951622926
-
Complementary resistive switches for passive nanocrossbar memories
-
May
-
E. Linn, R. Rosezin, C. Kügeler, and R. Waser, "Complementary resistive switches for passive nanocrossbar memories," Nat. Mater., vol. 9, no. 5, pp. 403-406, May 2010.
-
(2010)
Nat. Mater
, vol.9
, Issue.5
, pp. 403-406
-
-
Linn, E.1
Rosezin, R.2
Kügeler, C.3
Waser, R.4
-
25
-
-
3042808315
-
CMOS/nano co-design for crossbar-based molecular electronic systems
-
Dec
-
M. M. Ziegler andM. R. Stan, "CMOS/nano co-design for crossbar-based molecular electronic systems," IEEE Trans. Nanotechnol., vol. 2, no. 4, pp. 217-230, Dec. 2003.
-
(2003)
IEEE Trans. Nanotechnol
, vol.2
, Issue.4
, pp. 217-230
-
-
Ziegler, M.M.1
Stan, M.R.2
-
26
-
-
84948951350
-
Design and analysis of crossbar circuits for molecular nanoelectronics
-
M. M. Ziegler and M. R. Stan, "Design and analysis of crossbar circuits for molecular nanoelectronics," in Proc. 2nd Conf. IEEE-NANO, 2002, pp. 323-327.
-
(2002)
Proc. 2nd Conf. IEEE-NANO
, pp. 323-327
-
-
Ziegler, M.M.1
Stan, M.R.2
-
27
-
-
33751538494
-
A novel reference scheme for reading passive resistive crossbar memories
-
DOI 10.1109/TNANO.2006.885016
-
J. Mustafa and R. Waser, "A novel reference scheme for reading passive resistive crossbar memories," IEEE Trans. Nanotechnol., vol. 5, no. 6, pp. 687-691, Nov. 2006. (Pubitemid 44837050)
-
(2006)
IEEE Transactions on Nanotechnology
, vol.5
, Issue.6
, pp. 687-691
-
-
Mustafa, J.1
Waser, R.2
-
28
-
-
44849117666
-
Fundamental analysis of resistive nanocrossbars for the use in hybrid nano/CMOS-memory
-
A. Flocke and T. G. Noll, "Fundamental analysis of resistive nanocrossbars for the use in hybrid nano/CMOS-memory," in Proc. 33rd ESSCIRC, 2007, pp. 328-331.
-
(2007)
Proc. 33rd ESSCIRC
, pp. 328-331
-
-
Flocke, A.1
Noll, T.G.2
-
29
-
-
84864147795
-
Scaling challenges for the cross-point resistive memory array to sub-10 nm node-An interconnect perspective
-
J. Liang, S. Yeh, S. S. Wong, and H.-S. P. Wong, "Scaling challenges for the cross-point resistive memory array to sub-10 nm node-An interconnect perspective," in Proc. IEEE 4th IMW, 2012, pp. 1-4.
-
(2012)
Proc. IEEE 4th IMW
, pp. 1-4
-
-
Liang, J.1
Yeh, S.2
Wong, S.S.3
Wong, H.-S.P.4
-
30
-
-
77957010403
-
Cross-point memory array without cell selectors-Device characteristics and data storage pattern dependencies
-
Oct.
-
J. Liang and H.-S. P. Wong, "Cross-point memory array without cell selectors-Device characteristics and data storage pattern dependencies," IEEE Trans. Electron Devices, vol. 57, no. 10, pp. 2531-2538, Oct. 2010.
-
(2010)
IEEE Trans. Electron Devices
, vol.57
, Issue.10
, pp. 2531-2538
-
-
Liang, J.1
Wong, H.-S.P.2
-
31
-
-
70349665404
-
Writing to and reading from a nano-scale crossbar memory based on memristors
-
Oct. 21
-
P. O. Vontobel, W. Robinett, P. J. Kuekes, D. R. Stewart, J. Straznicky, and R. S. Williams, "Writing to and reading from a nano-scale crossbar memory based on memristors," Nanotechnology, vol. 20, no. 42, p. 425 204, Oct. 21, 2009.
-
(2009)
Nanotechnology
, vol.20
, Issue.42
, pp. 425204
-
-
Vontobel, P.O.1
Robinett, W.2
Kuekes, P.J.3
Stewart, D.R.4
Straznicky, J.5
Williams, R.S.6
-
32
-
-
84861192414
-
Analysis of passive memristive devices array: Data-dependent statistical model and self-adaptable sense resistance for RRAMs
-
Jun.
-
S. Shin, K. Kim, and S. M. Kang, "Analysis of passive memristive devices array: Data-dependent statistical model and self-adaptable sense resistance for RRAMs," Proc. IEEE, vol. 100, no. 6, pp. 2021-2032, Jun. 2012.
-
(2012)
Proc. IEEE
, vol.100
, Issue.6
, pp. 2021-2032
-
-
Shin, S.1
Kim, K.2
Kang, S.M.3
-
34
-
-
79952501265
-
An access-transistor-free (0T/1R) non-volatile resistance random access memory (RRAM) using a novel threshold switching, self-rectifying chalcogenide device
-
Y.-C. Chen, C. F. Chen, T. Chen, J. Y. Yu, S. Wu, S. L. Lung, R. Liu, and C.-Y. Lu, "An access-transistor-free (0T/1R) non-volatile resistance random access memory (RRAM) using a novel threshold switching, self-rectifying chalcogenide device," in IEDM Tech. Dig., 2003, pp. 37. 4. 1-37. 4. 4.
-
(2003)
IEDM Tech. Dig
, pp. 3741-3744
-
-
Chen, Y.-C.1
Chen, C.F.2
Chen, T.3
Yu, J.Y.4
Wu, S.5
Lung, S.L.6
Liu, R.7
Lu, C.-Y.8
-
35
-
-
36549083365
-
Two series oxide resistors applicable to high speed and high density nonvolatile memory
-
DOI 10.1002/adma.200700251
-
M. J. Lee, Y. Park, D. S. Suh, E. H. Lee, S. Seo, D. C. Kim, R. Jung, B. S. Kang, S. E. Ahn, C. B. Lee, D. H. Seo, Y. K. Cha, I. K. Yoo, J. S. Kim, and B. H. Park, "Two series oxide resistors applicable to high speed and high density nonvolatile memory," Adv. Mater., vol. 19, no. 22, pp. 3919-3923, Nov. 2007. (Pubitemid 350190438)
-
(2007)
Advanced Materials
, vol.19
, Issue.22
, pp. 3919-3923
-
-
Lee, M.-J.1
Park, Y.2
Suh, D.-S.3
Lee, E.-H.4
Seo, S.5
Kim, D.-C.6
Jung, R.7
Kang, B.-S.8
Ahn, S.-E.9
Lee, C.B.10
Seo, D.H.11
Cha, Y.-K.12
Yoo, I.-K.13
Kim, J.-S.14
Park, B.H.15
-
36
-
-
77952357088
-
A stackable cross point phase change memory
-
D. C. Kau, S. Tang, I. V. Karpov, R. Dodge, B. Klehn, J. A. Kalb, J. Strand, A. Diaz, N. Leung, J. Wu, S. Lee, T. Langtry, K.-W. Chang, C. Papagianni, J. Lee, J. Hirst, S. Erra, E. Flores, N. Righos, H. Castro, and G. Spadini, "A stackable cross point phase change memory," in IEDM Tech. Dig., 2009, pp. 617-620.
-
(2009)
IEDM Tech. Dig
, pp. 617-620
-
-
Kau, D.C.1
Tang, S.2
Karpov, I.V.3
Dodge, R.4
Klehn, B.5
Kalb, J.A.6
Strand, J.7
Diaz, A.8
Leung, N.9
Wu, J.10
Lee, S.11
Langtry, T.12
Chang, K.-W.13
Papagianni, C.14
Lee, J.15
Hirst, J.16
Erra, S.17
Flores, E.18
Righos, N.19
Castro, H.20
Spadini, G.21
more..
-
37
-
-
77957871741
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Highly-scalable novel access device based on mixed ionic electronic conduction (MIEC) materials for high density phase change memory (PCM) arrays
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K. Gopalakrishnan, R. S. Shenoy, C. T. Rettner, K. Virwani, D. S. Bethune, R. M. Shelby, G. W. Burr, A. Kellock, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, B. Jackson, A. M. Friz, T. Topuria, P. M. Rice, and B. N. Kurdi, "Highly-scalable novel access device based on mixed ionic electronic conduction (MIEC) materials for high density phase change memory (PCM) arrays," in Proc. VLSI Symp. Technol., 2010, pp. 205-206.
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(2010)
Proc. VLSI Symp. Technol
, pp. 205-206
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Gopalakrishnan, K.1
Shenoy, R.S.2
Rettner, C.T.3
Virwani, K.4
Bethune, D.S.5
Shelby, R.M.6
Burr, G.W.7
Kellock, A.8
King, R.S.9
Nguyen, K.10
Bowers, A.N.11
Jurich, M.12
Jackson, B.13
Friz, A.M.14
Topuria, T.15
Rice, P.M.16
Kurdi, B.N.17
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