An 8Mb multi-layered cross-point ReRAM macro with 443MB/s write throughput

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 432-433

  Kawahara, Akifumi ^a   Azuma, Ryotaro ^a   Ikeda, Yuuichirou ^a   Kawai, Ken ^a   Katoh, Yoshikazu ^a   Tanabe, Kouhei ^b   Nakamura, Toshihiro ^b   Sumimoto, Yoshihiko ^b   Yamada, Naoki ^b   Nakai, Nobuyuki ^b   Sakamoto, Shoji ^b   Hayakawa, Yukio ^a   Tsuji, Kiyotaka ^a   Yoneda, Shinichi ^a   Himeno, Atsushi ^a   Origasa, Ken Ichi ^b   Shimakawa, Kazuhiko ^a   Takagi, Takeshi ^a   Mikawa, Takumi ^a   Aono, Kunitoshi ^a  

^a Panasonic   (Japan)

^b Panasonic   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIT LINES; CELL ARRAY; EMBEDDED MEMORIES; HIGH-DENSITY; LOW VOLTAGES; MEMORY ARRAY; MEMORY CELL; MEMORY PERFORMANCE; MULTI-BITS; MULTI-LAYERED; NON-VOLATILE MEMORIES; WRITE OPERATIONS;

ELECTRIC ENERGY STORAGE; FLASH MEMORY; SEMICONDUCTOR STORAGE; VIRTUAL STORAGE;

MEMORY ARCHITECTURE;

EID: 84860664697     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6177078     Document Type: Conference Paper

References (4)

1. W. Otsuka, et al., "A 4Mb Conductive-Bridge Resistive Memory with 2.3GB/s Read-Throughput and 216MB/s Program-Throughput," ISSCC Dig. Tech. Papers, pp. 210-211, Feb. 2011.
2. C. J. Chevallier, et al., "A 0.13μm 64Mb Multi-Layered Conductive Metal-Oxide Memory," ISSCC Dig. Tech. Papers, pp. 260-261, Feb. 2010.
3. H. Chung, et al., "A 58nm 1.8V 1Gb PRAM with 6.4MB/s Program BW,"ISSCC Dig. Tech. Papers, pp. 500-502, Feb. 2011.
4. Z. Wei, et al., "Highly Reliable TaOx ReRAM and Direct Evidence of Redox Reaction Mechanism," IEDM Tech. Dig., pp. 293-296, Dec. 2008.