A primer on hardware security: Models, methods, and metrics

Proceedings of the IEEE

Volumn 102, Issue 8, 2014, Pages 1283-1295

  Rostami, Masoud ^a   Koushanfar, Farinaz ^a   Karri, Ramesh ^b  

^a Rice University   (United States)

^b POLYTECHNIC UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS; SUPPLY CHAINS;

EVALUATION METRICS; MULTI-STEP; STATE OF THE ART; THREAT MODELS;

HARDWARE SECURITY;

EID: 84905002818     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2014.2335155     Document Type: Article

References (111)

1. S. Skorobogatov, Hardware assurance and its importance to national security, 2012. [Online]. Available: Http://www.cl.cam.ac. uk/sps32/secnews.html
2. U.S. Department of Commerce, Defense industrial base assessment: Counterfeit electronics, 2010
3. 112th Congress, Inquiry into counterfeit electronic parts in the department of defense supply chain, Senate Report of the Committee on Armed Services, 2012
4. J. Grand, J. Applebaum, and C. Tarnovsky,Smart parking meter implementations, globalism, you aka meter maids eat their young, 2009. [Online]. Available: Https://www.defcon.org/images/defcon-17/ dc-17-presentations/defcon- 17-grandappelbaum-Tarnovsky-smart-parking.pdf
5. My Arduino can beat up your hotel room lock, 2012. [Online]. Available: Http://demoseen.com/bhpaper.html
6. A. Huang, Hacking the PIC 18F1320, 2007. [Online]. Available: Http://www. bunniestudios.com/blog/?page-id=40
7. Office of the Under Secretary of Defense For Acquisition, Technology, Logistics, Defense Science Board (DSB) study on high performance microchip supply, 2005. [Online]. Available: Www.acq.osd.mil/dsb/ reports/ADA435563.pdf
8. J. Roy, F. Koushanfar, and I. Markov, EPIC: Ending piracy of integrated circuits, IEEE Computer, vol. 43, no. 10, pp. 30-38, Oct. 2010
9. R. Torrance and D. James, The state-of-The-Art in semiconductor reverse engineering, in Proc. IEEE/ACM Design Autom. Conf., 2011, pp. 333-338
10. P. Kocher, J. Jaffe, and B. Jun, Differential power analysis, Adv. Cryptol., pp. 388-397, 1999
11. F. Koushanfar et al., Can EDA combat the rise of electronic counterfeiting? in Proc. IEEE/ACM Design Autom. Conf., 2012, pp. 133-138
12. SEMI, Innovation is at risk as semiconductor equipment and materials industry loses up to $4 billion annually due to IP infringement, 2008. [Online]. Available: Www.semi.org/en/Press/P043775
13. M. Rostami, F. Koushanfar, J. Rajendran, and R. Karri, Hardware security: Threat models and metrics, in Proc. Int. Conf. Comput.-Aided Design, 2013, pp. 819-823
14. F. Koushanfar and A. Mirhoseini, A unified framework for multimodal submodular integrated circuits trojan detection, IEEE Trans. Inf. Forensics Security, vol. 6, no. 1, pp. 162-174, Mar. 2011
15. R. Karri, J. Rajendran, K. Rosenfeld, and M. Tehranipoor, Trustworthy hardware: Identifying and classifying hardware trojans, IEEE Computer, vol. 43, no. 10, pp. 39-46, Oct. 2010
16. M. Tehranipoor and F. Koushanfar, A survey of hardware trojan taxonomy and detection, IEEE Design Test Comput., vol. 27, no. 1, pp. 10-25, Jan./Feb. 2010
17. E. Love, Y. Jin, and Y. Makris, Proof-carrying hardware intellectual property: A pathway to trusted module acquisition, IEEE Trans. Inf. Forensics Security, vol. 7, no. 1, pp. 25-40, Mar. 2012
18. A. Waksman and S. Sethumadhavan, Silencing hardware backdoors, in Proc. IEEE Symp. Security Privacy, 2011, pp. 49-63
19. M. Hicks, M. Finnicum, S. T. King, M. M. Martin, and J. M. Smith, Overcoming an untrusted computing base: Detecting and removing malicious hardware automatically, in Proc. IEEE Symp. Security Privacy, 2010, pp. 159-172
20. C. Sturton, M. Hicks, D. Wagner, and S. T. King, Defeating UCI: Building stealthy and malicious hardware, in Proc. IEEE Symp. Security Privacy, 2011, pp. 64-77
21. D. Agrawal, S. Baktir, D. Karakoyunlu, P. Rohatgi, and B. Sunar, Trojan detection using IC fingerprinting, in Proc. IEEE Symp. Security Privacy, 2007, pp. 296-310 (Pubitemid 47432536)
22. R. M. Rad, X. Wang, M. Tehranipoor, and J. Plusquellic, Power supply signal calibration techniques for improving detection resolution to hardware trojans, in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, 2008, pp. 632-639
23. Y. Jin and Y. Makris, Hardware trojan detection using path delay fingerprint, in Proc. IEEE Int. Workshop Hardware-Oriented Security Trust, 2008, pp. 51-57
24. M. Potkonjak, A. Nahapetian, M. Nelson, and T. Massey, Hardware Trojan horse detection using gate-level characterization, in Proc. IEEE/ACM Design Autom. Conf., 2009, pp. 688-693
25. Y. Alkabani and F. Koushanfar, Consistency-based characterization for IC Trojan detection, in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, 2009, pp. 123-127
26. K. Hu, A. N. Nowroz, S. Reda, and F. Koushanfar, High-sensitivity hardware trojan detection using multimodal characterization, in Proc. IEEE Design Autom. Test Eur. Conf. Exhibit., 2013, pp. 1271-1276
27. R. Chakraborty and S. Bhunia, HARPOON: An obfuscation-based SoC design methodology for hardware protection, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 28, no. 10, pp. 1493-1502, Oct. 2009
28. A. Kahng et al., Watermarking techniques for intellectual property protection, in Proc. IEEE/ACM Design Autom. Conf., 1998, pp. 776-781
29. Y. Alkabani and F. Koushanfar, Active hardware metering for intellectual property protection and security, in Proc. 16th USENIX Security Symp., 2007, pp. 291-306
30. F. Koushanfar, I. Hong, and M. Potkonjak, Behavioral synthesis techniques for intellectual property protection, ACM Trans. Design Autom. Electron. Syst., vol. 10, no. 3, pp. 523-545, 2005 (Pubitemid 43906372)
31. A. Kahng et al., Robust IP watermarking methodologies for physical design, in Proc. IEEE/ACM Design Autom. Conf., 1998, pp. 782-787
32. J. Lach, W. Mangione-Smith, and M. Potkonjak, FPGA fingerprinting techniques for protecting intellectual property, in Proc. IEEE Custom Integr. Circuits Conf., 1998, pp. 299-302
33. G. Wolfe, J. L. Wong, and M. Potkonjak, Watermarking graph partitioning solutions, in Proc. IEEE/ACM Design Autom. Conf., 2001, pp. 486-489 (Pubitemid 32841002)
34. C. Alpert and A. Kahng, Recent directions in netlist partitioning, Integration, VLSI J., vol. 19, no. 1-2, pp. 1-81, 1995
35. F. Koushanfar and Y. Alkabani, Provably secure obfuscation of diverse watermarks for sequential circuits, in Proc. IEEE Int. Symp. Hardware-Oriented Security Trust, 2010, pp. 42-47
36. A. Caldwell et al., Effective iterative techniques for fingerprinting design IP, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, no. 2, pp. 208-215, Feb. 2004
37. J. B. Wendt, F. Koushanfar, and M. Potkonjak, Techniques for foundry identification, in Proc. Design Autom. Conf., 2014, DOI: 10.1145/2593069.2593228
38. D. Holcomb, W. Burleson, and K. Fu, Power-up SRAM state as an identifying fingerprint and source of true random numbers, IEEE Trans. Comput., vol. 58, no. 9, pp. 1198-1210, Sep. 2009
39. Defense Advanced Research Projects Agency (DARPA), Supply Chain Hardware Integrity for Electronics Defense (SHIELD), Microsystems Technology Office/MTO Broad Agency Announcement, 2014
40. F. Koushanfar and R. Karri, Can the shield protect our integrated circuits? in Proc. Midwest Symp. Circuits Syst., 2014, pp. 51-57
41. M. Rostami, M. Majzoobi, F. Koushanfar, D. Wallach, and S. Devadas, Robust and reverse-engineering resilient puf authentication and key-exchange by substring matching, IEEE Trans. Emerging Topics Comput., vol. 2, no. 1, pp. 37-49, Mar. 2014
42. Y. Alkabani, F. Koushanfar, N. Kiyavash, and M. Potkonjak, Trusted integrated circuits: A nondestructive hidden characteristics extraction approach, Information Hiding, ser. Lecture Notes in Computer Science, Berlin, Germany: Springer-Verlag, 2008, vol. 5284, pp. 102-117
43. U. Ruhrmair, S. Devadas, and F. Koushanfar, Security based on physical unclonability and disorder Introduction to Hardware Security and Trust. New York, NY, USA: Springer-Verlag, 2011
44. J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri, Security analysis of logic obfuscation, in Proc. IEEE/ACM Design Autom. Conf., 2012, pp. 83-89
45. A. Baumgarten, A. Tyagi, and J. Zambreno, Preventing IC piracy using reconfigurable logic barriers, IEEE Design Test Comput., vol. 27, no. 1, pp. 66-75, Jan./Feb. 2010
46. Y. Alkabani, F. Koushanfar, and M. Potkonjak, Remote activation of ICs for piracy prevention and digital right management, in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, 2007, pp. 674-677
47. R. Chakraborty and S. Bhunia, RTL hardware IP protection using key-based control and data flow obfuscation, in Proc. IEEE Int. Conf. VLSI Design, 2010, pp. 405-410
48. R. Chakraborty and S. Bhunia, Hardware protection and authentication through netlist level obfuscation, in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, 2008, pp. 674-677
49. R. Chakraborty and S. Bhunia, Security against hardware trojan through a novel application of design obfuscation, in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, 2009, pp. 113-116
50. F. Koushanfar and G. Qu, Hardware metering, in Proc. IEEE/ACM Design Autom. Conf., 2001, pp. 490-493 (Pubitemid 32841003)
51. F. Koushanfar, Provably secure active IC metering techniques for piracy avoidance and digital rights management, IEEE Trans. Inf. Forensics Security, vol. 7, no. 1, pp. 51-63, Feb. 2012
52. F. Koushanfar, G. Qu, and M. Potkonjak, Intellectual property metering, in Proc. Inf. Hiding Workshop, 2001, pp. 81-95 (Pubitemid 33367660)
53. Intelligence Advanced Research Projects Activity (IARPA), Trusted integrated circuits program, 2011. [Online]. Available: Https://www.fbo.gov/ utils/view?id= b8be3d2c5d5babbdffc6975c370247a6
54. R. Jarvis and M. G. McIntyre, Split manufacturing method for advanced semiconductor circuits, U.S. Patent 7 195 931, 2004
55. B. Hill, R. Karmazin, C. Otero, J. Tse, and R. Manohar, A split-foundry asynchronous FPGA, in Proc. IEEE Custom Integr. Circuits Conf., 2013, DOI: 10.1109/CICC.2013.6658536
56. J. Rajendran, O. Sinanoglu, and R. Karri, Is split manufacturing secure? in Proc. IEEE Design Autom. Test Eur. Conf. Exhibit., 2013, pp. 1259-1264
57. J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri, Logic encryption: A fault analysis perspective, in Proc. IEEE Design Autom. Test Eur. Conf. Exhibit., 2012, pp. 953-958
58. Chipworks, Intels 22-nm tri-gate transistors exposed, 2012. [Online]. Available: Http://www.chipworks.com/blog/ technologyblog/2012/04/23/intels-22- nmtri-gate-Transistors-exposed/.
59. Defense Advanced Research Projects Agency (DARPA), Integrity and reliability of integrated circuits (IRIS), 2012. [Online]. Available: Http://www.darpa.mil/Our- Work/MTO/Programs/Integrity-and- ReliabilityofI ntegratedCircuits-.
60. ExtremeTech, iPhone 5 A6 SoC reverse engineered, reveals rare hand-made custom CPU, tri-core GPU. [Online]. Available: Http://tinyurl.com/9yn23he
61. Chipworks, Reverse engineering software. [Online]. Available: Http://www.chipworks. com/en/technical-competitive-Analysis/ resources/reverse-engineering-software
62. Degate. [Online]. Available: Http://www. degate.org/documentation/
63. W. M. V. Fleet and M. R. Dransfield, Method of recovering a gate-level netlist from a transistor-level, U.S. Patent 6 190 433, 1998
64. M. Hansen, H. Yalcin, and J. Hayes, Unveiling the ISCAS-85 benchmarks: A case study in reverse engineering, IEEE Design Test Comput., vol. 16, no. 3, pp. 72-80, May/Jun. 1999 (Pubitemid 30497933)
65. W. Li, Z. Wasson, and S. Seshia, Reverse engineering circuits using behavioral pattern mining, in Proc. IEEE Int. Symp. Hardware-Oriented Security Trust, 2012, pp. 83-88
66. P. Subramanyan et al., Reverse engineering digital circuits using functional analysis, in Proc. IEEE Design Autom. Test Eur. Conf. Exhibit., 2013, pp. 1277-1280
67. SypherMedia, Syphermedia library circuit camouflage technology. [Online]. Available: Http://www.smi.tv/solutions.htm
68. J. P. Baukus, L. W. Chow, R. P. Cocchi, and B. J. Wang, Method and apparatus for camouflaging a standard cell based integrated circuit with micro circuits and post processing, U.S. Patent 2012 0 139 582, 2012
69. J. P. Baukus, L. W. Chow, R. P. Cocchi, P. Ouyang, and B. J. Wang, Building block for a secure CMOS logic cell library, U.S. Patent 8 111 089, 2012
70. J. P. Baukus, L. W. Chow, and W. Clark, Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide, U.S. Patent 2002 0 096 776, 2002
71. J. P. Baukus, L. W. Chow, R. P. Cocchi, P. Ouyang, and B. J. Wang, Camouflaging a standard cell based integrated circuit, U.S. Patent 8 151 235, 2012
72. J. Rajendran, M. Sam, O. Sinanoglu, and R. Karri, Security analysis of integrated circuit camouflaging, in Proc. ACM Conf. Comput. Commun. Security, 2013, pp. 709-720
73. J. Rajendran, O. Sinanoglu, and R. Karri, VLSI testing based security metric for IC camouflaging, in Proc. IEEE Int. Test Conf., 2013, DOI: 10.1109/TEST.2013.6651879
74. P. Rohatgi, Improved techniques for side-channel analysis, Cryptographic Engineering. New York, NY, USA: Springer-Verlag, 2009, pp. 381-406
75. C. Paar, J. Pelzl, and B. Preneel, Understanding Cryptography: A Textbook for Students and Practitioners. New York, NY, USA: Springer-Verlag, 2010
76. F. Koeune and F.-X. Standaert, A tutorial on physical security and side-channel attacks Foundations of Security Analysis and Design III. Berlin, Germany: Springer-Verlag, 2005, pp. 78-108
77. P. Rohatgi, Electromagnetic attacks and countermeasures, Cryptographic Engineering. Berlin, Germany: Springer-Verlag, 2009, pp. 407-430
78. A. Schlösser, D. Nedospasov, J. Krämer, S. Orlic, and J.-P. Seifert, Simple photonic emission analysis of AES, J. Cryptogr. Eng., vol. 3, no. 1, pp. 3-15, 2013
79. D. Genkin, A. Shamir, and E. Tromer, RSA key extraction via low-bandwidth acoustic cryptanalysis, Cryptology ePrint Archive, Rep. 2013/857, 2013
80. H. Bar-El, H. Choukri, D. Naccache, M. Tunstall, and C. Whelan, The sorcerers apprentice guide to fault attacks, Proc. IEEE, vol. 94, no. 2, pp. 370-382, Feb. 2006 (Pubitemid 43145991)
81. B. Yang, K. Wu, and R. Karri, Scan based side channel attack on dedicated hardware implementations of data encryption standard, in Proc. Int. Test Conf., 2004, pp. 339-344 (Pubitemid 40610032)
82. J. Lee, M. Tehranipoor, C. Patel, and J. Plusquellic, Securing designs against scan-based side-channel attacks, IEEE Trans. Dependable Secure Comput., vol. 4, no. 4, pp. 325-336, Oct.-Dec. 2007 (Pubitemid 350125897)
83. M. Agrawal, S. Karmakar, D. Saha, and D. Mukhopadhyay, Scan based side channel attacks on stream ciphers and their counter-measures, in Proc. INDOCRYPT, 2008, pp. 226-238
84. D. Merli, D. Schuster, F. Stumpf, and G. Sigl, Side-channel analysis of PUFs and fuzzy extractors, Trust and Trustworthy Computing. New York, NY, USA: Springer-Verlag, 2011, pp. 33-47
85. U. Rührmair et al., Power and timing side channels for PUFs and their efficient exploitation, Cryptology ePrint Archive, Rep. 2013/851, 2013
86. D. Karakoyunlu and B. Sunar, Differential template attacks on PUF enabled cryptographic devices, in Proc. Int. Workshop Inf. Forensics Security, 2010, DOI: 10.1109/WIFS.2010.5711445
87. A. Mahmoud, U. Rührmair, M. Majzoobi, and F. Koushanfar, Combined modeling and side channel attacks on strong PUFs, Cryptology ePrint Archivetx, Rep. 2013/632, 2013. [Online]. Available: Http://eprint.iacr.org/.
88. B. Kopf and D. Basin, An information-Theoretic model for adaptive side-channel attacks, in Proc. ACM Conf. Comput. Commun. Security, 2007, pp. 286-296
89. P. Rakers, L. Connell, T. Collins, and D. Russell, Secure contactless smartcard ASIC with DPA protection, J. Solid-State Circuits, vol. 36, no. 3, pp. 559-565, Mar. 2001 (Pubitemid 32302998)
90. K. Tiri, M. Akmal, and I. Verbauwhede, A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards, in Proc. Eur. Solid-State Circuits Conf., 2002, pp. 403-406
91. S. Moore, R. Anderson, R. Mullins, G. Taylor, and J. J. Fournier, Balanced self-checking asynchronous logic for smart card applications, Microprocess. Microsyst., vol. 27, no. 9, pp. 421-430, 2003
92. F. Mace, F.-X. Standaert, I. Hassoune, J.-D. Legat, and J.-J. Quisquater, A dynamic current mode logic to counteract power analysis attacks, in Proc. Int. Conf. Design Circuits Integr. Syst., 2004, pp. 186-191
93. M. Stanojlovic and P. Petkovic, Strategies against side-channel-Attack, in Proc. Small Syst. Simul. Symp., 2010, pp. 86-89
94. M. Joye, Basics of side-channel analysis, Cryptographic Engineering. Berlin, Germany: Springer-Verlag, 2009, pp.365-380
95. P. Kocher, J. Jaffe, B. Jun, and P. Rohatgi, Introduction to differential power analysis, J. Cryptogr. Eng., vol. 1, no. 1, pp. 5-27, 2011
96. C. Clavier, J.-S. Coron, and N. Dabbous, Differential power analysis in the presence of hardware countermeasures, Cryptographic Hardware and Embedded Systems, vol. 1965. Berlin, Germany: Springer-Verlag, 2000, pp. 252-263, ser. Lecture Notes in Computer Science (Pubitemid 33213973)
97. P. C. Kocher, Leak-resistant cryptographic indexed key update, U.S. Patent 6 539 092, 2003
98. J. Demme, R. Martin, A. Waksman, and S. Sethumadhavan, Side-channel vulnerability factor: A metric for measuring information leakage, in Proc. IEEE Int. Symp. Comput. Architect., 2012, pp. 106-117
99. J. Katz and V. Vaikuntanathan, Signature schemes with bounded leakage resilience, Advances in Cryptology, vol. 5912. Berlin, Germany: Springer-Verlag, 2009, pp. 703-720, ser. Lecture Notes in Computer Science
100. Y. Yu, F.-X. Standaert, O. Pereira, and M. Yung, Practical leakage-resilient pseudorandom generators, in Proc. ACM Conf. Comput. Commun. Security, 2010, pp. 141-151
101. F.-X. Standaert, O. Pereira, Y. Yu, J.-J. Quisquater, M. Yung, and E. Oswald, Leakage resilient cryptography in practice, Towards Hardware-Intrinsic Security. Berlin, Germany: Springer-Verlag, 2010, pp. 99-134, ser. Information Security and Cryptography
102. B. Yang, K. Wu, and R. Karri, Secure scan: A design-for-Test architecture for crypto chips, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 10, pp. 2287-2293, Oct. 2006
103. D. Boneh, Cryptography I, 2013. [Online]. Available: Https://class. coursera.org/ crypto-007/class/index
104. L. Domnitser, N. Abu-Ghazaleh, and D. Ponomarev, A predictive model for cache-based side channels in multicore and multithreaded microprocessors, Computer Network Security, vol. 6258. Berlin, Germany: Springer-Verlag, 2010, pp. 70-85, ser. Lecture Notes in Computer Science
105. J.-S. Coron, P. Kocher, and D. Naccache, Statistics and secret leakage, Financial Cryptography, vol. 1962. Berlin, Germany: Springer-Verlag, 2001, pp. 157-173, ser. Lecture Notes in Computer Science (Pubitemid 33359604)
106. Y. Alkabani and F. Koushanfar, Active hardware metering for intellectual property protection and security, in Proc. USENIX Security Symp., 2007, pp. 291-306
107. V. Huard, M. Denais, and C. Parthasarathy, NBTI degradation: From physical mechanisms to modelling, Microelectron. Reliab., vol. 46, no. 1, pp. 1-23, 2006 (Pubitemid 41774239)
108. K. Chatterjee and D. Das, Semiconductor manufacturers efforts to improve trust in the electronic part supply chain, IEEE Trans. Compon. Packag. Technol., vol. 30, no. 3, pp. 547-549, Sep. 2007
109. S. Wei, A. Nahapetian, and M. Potkonjak, Quantitative intellectual property protection using physical-level characterization, IEEE Trans. Inf. Forensics Security, vol. 8, no. 11, pp. 1722-1730, Nov. 2013
110. K. Huang, J. Carulli, and Y. Makris, Parametric counterfeit IC detection via support vector machines, in Proc. IEEE Int. Symp. Defect Fault Tolerance VLSI Nanotechnol. Syst., 2012, pp. 7-12
111. X. Zhang, K. Xiao, and M. Tehranipoor, Path-delay fingerprinting for identification of recovered ICs, in Proc. IEEE Int. Symp. Defect Fault Tolerance VLSI Nanotechnol. Syst., 2012, pp. 13-18