Unveiling the ISCAS-85 benchmarks: a case study in reverse engineering

IEEE Design and Test of Computers

Volumn 16, Issue 3, 1999, Pages 72-80

  Hansen, Mark C ^a   Yalcin, Hakan ^b   Hayes, John P ^c,d,e  

^a DELPHI CORPORATION   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

^c UNIVERSITY OF MICHIGAN   (United States)

^d NATIONAL UNIVERSITY OF IRELAND   (Ireland)

^e University of Michigan   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; BENCHMARKING; BOOLEAN FUNCTIONS; COMPUTER AIDED DESIGN; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LOGIC CIRCUITS; LOGIC DESIGN; NAND CIRCUITS; VLSI CIRCUITS;

CARRY LOOK AHEAD; ERROR CORRECTING CIRCUITS; REGISTER TRANSFER;

REVERSE ENGINEERING;

EID: 0033359923     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.785838     Document Type: Article

References (12)

1. F. Brglez and H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits," Proc. IEEE Int'l Symp. Circuits and Systems, IEEE Press, Piscataway, N.J., 1985, pp. 695-698; see also the ISCAS-85 benchmark directory at http://www.cbl.ncsu.edu/benchmarks.
2. M.C. Hansen and J.P. Hayes, "High-Level Test Generation Using Physically Induced Faults," Proc. VLSI Test Symp., IEEE Computer Soc. Press, Los Alamitos, Calif., 1995, pp. 20-28.
3. E.J. Chikofsky and J.H. Cross, "Reverse Engineering and Design Recovery: A Taxonomy," IEEE Software, Vol. 7, No. 3, Mar. 1990, pp. 13-17.
4. S. Kundu, "GateMaker: A Transistor to Gate Level Model Extractor for Simulation, Automatic Test Pattern Generation and Verification," Proc. IEEE Int'l Test Conf., IEEE CS Press, 1998, pp. 372-381.
5. N.H.E. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, 2nd ed., Addison-Wesley, Reading, Mass., 1992.
6. C.L. Chen and M.Y. Hsiao, "Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review," IBM J. Research and Development, Vol. 28, Mar. 1984, pp. 124-134.
7. F. Brglez, D. Bryan, and K. Kozminski, "Combinational Profiles of Sequential Benchmark Circuits," Proc. IEEE Int'l Symp. Circuits and Systems, IEEE Press, 1989, pp. 1,929-1,934.
8. Y. Kukimoto et al., "Approximate Timing Analysis of Combinational Circuits Under the XBD0 Model," Proc. Int'l Conf. Computer-Aided Design, IEEE CS Press, 1997, pp. 176-181.
9. H. Yalcin and J.P. Hayes, "Hierarchical Timing Analysis Using Conditional Delays," Proc. Int'l Conf. Computer-Aided Design, IEEE CS Press, 1995, pp. 371-377.
10. A. Chowdhary and J.P. Hayes, "General Modeling and Technology-Mapping Technique for LUT-Based FPGAs," Proc. Fifth Int'l Symp. FPGAs, ACM Press, New York, 1997, pp. 43-47.
11. M.C. Hansen and J.P. Hayes, "High-Level Test Generation Using Symbolic Scheduling," Proc. IEEE Int'l Test Conf., IEEE CS Press, 1995, pp. 586-595.
12. H. Yalcin, J.P. Hayes, and K.A. Sakallah, "An Approximate Timing Analysis Method for Datapath Circuits," Proc. Int'l Conf. Computer-Aided Design, IEEE CS Press, 1996, pp. 114-118.