A survey of hardware trojan taxonomy and detection

IEEE Design and Test of Computers

Volumn 27, Issue 1, 2010, Pages 10-25

  Tehranipoor, Mohammad ^a   Koushanfar, Farinaz ^b  

^a UNIVERSITY OF TEXAS AT DALLAS   (United States)

^b RICE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

TROJANS;

TAXONOMIES;

SURVEYS;

EID: 76949093207     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2010.7     Document Type: Review

References (34)

1. "Report of the Defense Science Board Task Force on High Performance Microchip Supply," Defense Science Board, US DoD, Feb. 2005; http://www.acq.osd.mil/dsb/ reports/2005-02-HPMS-Report-Final.pdf.
2. J. Lieberman, "National Security Aspects of the Global Migration of the U.S. Semiconductor Industry," white paper, Airland Subcommittee, US Senate Armed Services Committee, June 2003; http://lieberman.senate. gov/documents/whitepapers/semiconductor.pdf.
3. S. Adee, "The Hunt for the Kill Switch," IEEE Spectrum, vol.45, no.5, 2008, pp. 34-39.
4. "Innovation at Risk-Intellectual Property Challenges and Opportunities," white paper, Semiconductor Equipment and Materials International, June 2008.
5. X. Wang, M. Tehranipoor, and J. Plusquellic, "Detecting Malicious Inclusions in Secure Hardware: Challenges and Solutions," Proc. IEEE Int'l Workshop Hardware- Oriented Security and Trust (HOST 08), IEEE CS Press, 2008, pp. 15-19.
6. F. Wolff et al., "Towards Trojan Free Trusted ICs: Problem Analysis and Detection Scheme," Proc. Design, Automation and Test in Europe Conf. (DATE 08), ACM Press, 2008, pp. 1362-1365.
7. Y. Alkabani and F. Koushanfar, "Extended Abstract: Designer's Hardware Trojan Horse," Proc. IEEE Int'l Workshop Hardware-Oriented Security and Trust (HOST 08), IEEE CS Press, 2008, pp. 82-83.
8. Y. Jin, N. Kupp, and Y. Makris, "Experiences in Hardware Trojan Design and Implementation," Proc. IEEE Int'l Workshop Hardware-Oriented Security and Trust (HOST 09), IEEE CS Press, 2009, pp. 50-57.
9. X. Wang et al., "Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis," Proc. IEEE Int'l Symp. Defect and Fault Tolerance of VLSI Systems (DFT 08), IEEE CS Press, 2008, pp. 87-95.
10. R. Rad et al., "Power Supply Signal Calibration Techniques for Improving Detection Resolution to Hardware Trojans," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD 08), IEEE CS Press, 2008, pp. 632-639.
11. S. King et al., "Designing and Implementing Malicious Hardware," Proc. 1st USENIX Workshop Large-Scale Exploits and Emergent Threats (LEET 08), Usenix Assoc., 2008, pp. 1-8.
12. Y. Alkabani and F. Koushanfar, "Active Hardware Metering for Intellectual Property Protection and Security," Proc. 16th USENIX Security Symp., Usenix Assoc., 2007, pp. 291-306.
13. D. Agrawal et al., "Trojan Detection Using IC Fingerprinting," Proc. IEEE Symp. Security and Privacy (SP 07), IEEE CS Press, 2007, pp. 296-310.
14. Y. Alkabani and F. Koushanfar, "Consistency-Based Characterization for IC Trojan Detection," Proc. IEEE/ ACM Int'l Conf. Computer-Aided Design (ICCAD 09), IEEE CS Press, 2009.
15. M. Potkonjak et al., "Hardware Trojan Horse Detection Using Gate-Level Characterization," Proc. 46th Design Automation Conf. (DAC 09), ACM Press, 2009, pp. 688-693.
16. J. Li and J. Lach, "At-Speed Delay Characterization for IC Authentication and Trojan Horse Detection," Proc. IEEE Int'l Workshop Hardware-Oriented Security and Trust (HOST 08), IEEE CS Press, 2008, pp. 8-14.
17. Y. Jin and Y. Makris, "Hardware Trojan Detection Using Path Delay Fingerprint," Proc. IEEE Int'l Hardware- Oriented Security and Trust (HOST 08), IEEE CS Press, 2008, pp. 51-57.
18. S. Jha and S.K. Jha, "Randomization Based Probabilistic Approach to Detect Trojan Circuits," Proc. 11th IEEE High Assurance Systems Engineering Symp., IEEE CS Press, 2008, pp. 117-124.
19. M. Banga and M. Hsiao, "A Region Based Approach for the Identification of Hardware Trojans," Proc. IEEE Int'l Workshop Hardware-Oriented Security and Trust (HOST 08), IEEE CS Press, 2008, pp. 40-47.
20. M. Banga and M. Hsiao, "A Novel Sustained Vector Technique for the Detection of Hardware Trojans," Proc. 22nd Int'l Conf. VLSI Design, IEEE CS Press, 2009, pp. 327-332.
21. I. Verbauwhede and P. Schaumont, "Design Methods for Security and Trust," Proc. Design, Automation and Test in Europe Conf. (DATE 07), EDA Consortium, pp. 672-677.
22. G.E. Suh, D. Deng, and A. Chan, "Hardware Authentication Leveraging Performance Limits in Detailed Simulations and Emulations," Proc. 46th Design Automation Conf. (DAC 09), ACM Press, 2009, pp. 682-687.
23. G. Bloom, B. Narahari, and R. Simha, "OS Support for Detecting Trojan Circuit Attacks," Proc. IEEE Int'l Workshop Hardware-Oriented Security and Trust (HOST 09), IEEE CS Press, 2009, pp. 100-103.
24. D. McIntyre et al., "Dynamic Evaluation of Hardware Trust," Proc. IEEE Int'l Workshop Hardware-Oriented Security and Trust (HOST 09), IEEE CS Press, 2009, pp. 108-111.
25. H. Salmani, M. Tehranipoor, and J. Plusquellic, "New Design Strategy for Improving Hardware Trojan Detection and Reducing Trojan Activation Time," Proc. IEEE Workshop Hardware-Oriented Security and Trust (HOST 09), IEEE CS Press, 2009, pp. 66-73.
26. M. Banga and M. Hsiao, "VITAMIN: Voltage Inversion Technique to Ascertain Malicious Insertion in ICs," Proc. 2nd IEEE Int'l Workshop Hardware-Oriented Security and Trust (HOST 09), IEEE CS Press, 2009, pp. 104-107.
27. M. Abramovici and P. Bradley, "Integrated Circuit Security: New Threats and Solutions," Proc. 5th Ann. Workshop Cyber Security and Information Intelligence Research: Cyber Security and Information Challenges and Strategies (CSIIRW 09), ACM Press, 2009, article 55.
28. R.S. Chakraborty, S. Paul, and S. Bhunia, "On- Demand Transparency for Improving Hardware Trojan Detectability," Proc. IEEE Int'l Workshop Hardware- Oriented Security and Trust (HOST 08), IEEE CS Press, 2008, pp. 48-50.
29. G. Qu and M. Potkonjak, Intellectual Property Protection in VLSI Designs: Theory and Practice, Kluwer Academic Publishers, 2003.
30. B. Gassend et al., "Identification and Authentication of Integrated Circuits: Research Articles," Concurrency and Computation: Practice & Experience, vol.16, no.11, 2004, pp. 1077-1098.
31. U. Rürmair, J. Söter, and F. Sehnke, "On the Foundations of Physical Unclonable Functions," Cryptology ePrint Archive, report 2009/277, 10 June 2009; http:// eprint.iacr.org/2009/277.pdf.
32. M. Majzoobi, F. Koushanfar, and M. Potkonjak, "Techniques for Design and Implementation of Secure Reconfigurable PUFs," ACM Trans. Reconfigurable Technology and Systems, vol.2, no.1, 2009, article 5.
33. M. Majzoobi, F. Koushanfar, and M. Potkonjak, "Testing Techniques for Hardware Security," Proc. Int'l Test Conf. (ITC 08), IEEE CS Press, 2008, pp. 1-10.
34. S. Trimberger, "Trusted Design in FPGAs," Proc. 44th Design Automation Conf. (DAC 07), ACM Press, 2007, pp. 5-8.