Security analysis of integrated circuit camouflaging

Proceedings of the ACM Conference on Computer and Communications Security

Volumn , Issue , 2013, Pages 709-720

  Rajendran, Jeyavijayan ^a   Sam, Michael ^a   Sinanoglu, Ozgur ^b   Karri, Ramesh ^a  

^a POLYTECHNIC UNIVERSITY   (United States)

^b NEW YORK UNIVERSITY ABU DHABI   (United Arab Emirates)

Author keywords

ic camouflaging; ic reverse engineering; ip piracy; ip protection

Indexed keywords

BENCHMARK CIRCUIT; IC TESTING; IP PIRACIES; IP PROTECTION; NETLIST; SECURITY ANALYSIS; SELECT GATE; STANDARD CELL;

REVERSE ENGINEERING;

SECURITY OF DATA;

EID: 84889058172     PISSN: 15437221     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2508859.2516656     Document Type: Conference Paper

References (39)

1. Chipworks, "Intel's 22-nm Tri-gate Transistors Exposed," http://www.chipworks.com/blog/technologyblog/2012/04/23/intels-22-nm-tri-gate- transistors-exposed/, 2012.
2. R. Torrance and D. James, "The state-of-the-art in semiconductor reverse engineering," in the Proc. of IEEE/ACM Design Automation Conference, pp. 333-338, 2011.
3. ExtremeTech, "iPhone 5 A6 SoC reverse engineered, reveals rare hand-made custom CPU, and tri-core GPU," http://www.extremetech.com/ computing/136749-iphone-5-a6-soc-reverse-engineered-reveals-rare-hand-made- custom-cpu-and-a-tri-core-gpu.
4. Silicon Zoo, "The layman's guide to ic reverse engineering," http://siliconzoo.org/tutorial.html.
5. Chipworks, "Reverse engineering software," http://www. chipworks.com/en/technical-competitive-analysis/resources/reerse-engineering- software.
6. Degate, http://www.degate.org/documentation/.
7. SEMI, "Innovation is at risk as semiconductor equipment and materials industry loses up to $4 billion annually due to IP infringement," www.semi.org/en/Press/P043775, 2008.
8. SypherMedia, "Syphermedia library circuit camouflage technology," http://www.smi.tv/solutions.htm.
9. J. P. Baukus, L. W. Chow, R. P. Cocchi, and B. J. Wang, "Method and apparatus for camouflaging a standard cell based integrated circuit with micro circuits and post processing," US Patent no. 20120139582, 2012.
10. J. P. Baukus, L. W. Chow, R. P. Cocchi, P. Ouyang, and B. J. Wang, "Building block for a secure cmos logic cell library," US Patent no. 8111089, 2012.
11. J. P. Baukus, L. W. Chow, and W. Clark, "Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide," US Patent no. 20020096776, 2002.
12. "Sun Microsystems, OpenSPARC T1 Processor," http://www.opensparc.net/opensparc-t1/index.html.
13. J. P. Baukus, L. W. Chow, R. P. Cocchi, P. Ouyang, and B. J. Wang, "Camouflaging a standard cell based integrated circuit," US Patent no. 8151235, 2012.
14. J. P. Baukus, L.-W. Chow, J. W. M. Clark, and G. J. Harbison, "Conductive channel pseudo block process and circuit to inhibit reverse engineering," US Patent no. 8258583, 2012.
15. M. L. Bushnell and V. D. Agrawal, "Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits," Kluwer Academic Publishers, Boston, 2000.
16. M. Abramovici, M. A. Breuer, and A. D. Friedman, "Digital Systems Testing & Testable Design," Wiley, 1994.
17. M. Hansen, H. Yalcin, and J. Hayes, "Unveiling the ISCAS-85 benchmarks: a case study in reverse engineering," IEEE Design Test of Computers, vol. 16, no. 3, pp. 72-80, 1999.
18. H. Lee and D. S. Ha, "HOPE: An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 9, pp. 1048-1058, 1996.
19. Cadence, "RTL Compiler," www.cadence.com/products/ld/rtl- compiler.
20. K. Constantinides, "Online low-cost defect tolerance solutions for microprocessor designs," web.eecs.umich.edu/ taustin/papers/Kypros-Thesis. pdf.
21. A. Waksman, J. Eum, and S. Sethumadhavan, "Practical, lightweight secure inclusion of third-party intellectual property," IEEE Design & Test, no. 99, pp. 1-1, 2013.
22. Oracle, "Opensparc internals," http://www.oracle.com/ technetwork/systems/opensparc/opensparc-internals-book-1500271.pdf.
23. Y. Alkabani and F. Koushanfar, "Active hardware metering for intellectual property protection and security," in the Proc. of USENIX security, pp. 291-306, 2007.
24. H. Heys and S. Tavares, "Avalanche characteristics of substitution-permutation encryption networks," IEEE Transactions on Computers, vol. 44, no. 9, pp. 1131-1139, 1995.
25. R. Torrance and D. James, "The state-of-the-art in ic reverse engineering," in the Proc. of Cryptographic Hardware and Embedded Systems, pp. 363-381, 2009.
26. W. M. V. Fleet and M. R. Dransfield, "Method of recovering a gate-level netlist from a transistor-level," US Patent no. 6190433, 1998.
27. W. Li, Z. Wasson, and S. Seshia, "Reverse engineering circuits using behavioral pattern mining," in the Proc. of IEEE International Symposium on Hardware-Oriented Security and Trust, pp. 83-88, 2012.
28. P. Subramanyan, N. Tsiskaridze, K. Pasricha, D. Reisman, A. Susnea, and S. Malik, "Reverse engineering digital circuits using functional analysis," in the Proc. of IEEE/ACM Design Automation and Test in Europe, 2013.
29. R. Chakraborty and S. Bhunia, "HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 10, pp. 1493-1502, 2009.
30. J. Roy, F. Koushanfar, and I. Markov, "EPIC: Ending Piracy of Integrated Circuits," IEEE Computer, vol. 43, no. 10, pp. 30-38, 2010.
31. J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri, "Security analysis of logic obfuscation," in the Proc. of IEEE/ACM Design Automation Conference, pp. 83-89, 2012.
32. -, "Logic encryption: A fault analysis perspective," IEEE Design, Automation Test in Europe, pp. 953-958, 2012.
33. A. Baumgarten, A. Tyagi, and J. Zambreno, "Preventing IC Piracy Using Reconfigurable Logic Barriers," IEEE Design and Test of Computers, vol. 27, no. 1, pp. 66-75, 2010.
34. A. Kahng, J. Lach, W. Mangione-Smith, S. Mantik, I. Markov, M. Potkonjak, P. Tucker, H. Wang, and G. Wolfe, "Watermarking techniques for intellectual property protection," in the Proc. of IEEE/ACM Design Automation Conference, pp. 776-781, 1998.
35. F. Koushanfar, I. Hong, and M. Potkonjak, "Behavioral synthesis techniques for intellectual property protection," ACM Transactions on Design Automation of Electronic Systems, vol. 10, no. 3, pp. 523-545, 2005.
36. A. Kahng, S. Mantik, I. Markov, M. Potkonjak, P. Tucker, H. Wang, and G. Wolfe, "Robust IP watermarking methodologies for physical design," in the Proc. of IEEE/ACM Design Automation Conference, pp. 782-787, 1998.
37. G. Suh and S. Devadas, "Physical Unclonable Functions for Device Authentication and Secret Key Generation," in the Proc. of the IEEE/ACM Design Automation Conference, pp. 9-14, 2007.
38. J. Lee, D. Lim, B. Gassend, G. Suh, M. van Dijk, and S. Devadas, "A technique to build a secret key in integrated circuits for identification and authentication applications," in the Proc. of IEEE Internationall Symposium on VLSI Circuits, pp. 176-179, 2004.
39. Cadence, "SoC Encounter," http://www.cadence.com/products/di/ soc-encounter/ pages/default.aspx.