Can EDA combat the rise of electronic counterfeiting?

Proceedings - Design Automation Conference

Volumn , Issue , 2012, Pages 133-138

  Koushanfar, Farinaz ^a   Fazzari, Saverio ^b   McCants, Carl ^c   Bryson, William ^d   Sale, Matthew ^e   Song, Peilin ^f   Potkonjak, Miodrag ^g  

^a RICE UNIVERSITY   (United States)

^b BOOZ ALLEN HAMILTON   (United States)

^c DEFENSE ADVANCED RESEARCH PROJECTS AGENCY   (United States)

^d Analytical Solutions Inc   (United States)

^e NAVAL SURFACE WARFARE CENTER   (United States)

^f IBM RESEARCH   (United States)

^g UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

counterfeiting; device and IC aging; reliability

Indexed keywords

CAN TECHNOLOGY; COUNTERFEITING; DESIGN PHASE; DETECTION TOOLS; GLOBAL PROBLEMS; IP PROTECTION; SEMICONDUCTOR COMPANIES; SEMICONDUCTOR INDUSTRY; TECHNICAL CHALLENGES; TEST PART;

RELIABILITY; SEMICONDUCTOR DEVICE MANUFACTURE;

COMPUTER AIDED DESIGN;

EID: 84863550104     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2228360.2228386     Document Type: Conference Paper

References (39)

1. Y. Alkabani and F. Koushanfar. "Active Hardware Metering for Intellectual Property Protection and Security" USENIX Security, pp. 291-306, 2007.
2. A. Caldwell et al., "Effective iterative techniques for fingerprinting design IP," IEEE T-CAD, vol. 23, no. 2, pp. 208-215, 2004.
3. A. Kahng et al., "Copy detection for intellectual property protection of VLSI designs," ICCAD, pp. 600-604, 1999.
4. F. Koushanfar, G. Qu, and M. Potkonjak, "Intellectual property metering," IH, pp. 81-95, 2001.
5. F. Koushanfar and M. Potkonjak, "CAD-based security, cryptography, and digital rights management," DAC, pp. 268-269, 2007.
6. Y. Alkabani et al. "Trusted integrated circuits: a nondestructive hidden characteristics extraction approach," IH, pp. 102-117, 2008.
7. S. Wei, S. Meguerdichian, and M. Potkonjak, "Gate-level characterization: foundations and hardware security applications," DAC, pp. 222-227, 2010.
8. S. Wei, A. Nahapetian, and M. Potkonjak, "Robust passive hardware metering," ICCAD, pp. 802-809, 2011.
9. R. Chau et al., "High-k/metal-gate stack and its MOSFET characteristics," IEEE EDL, vol. 25, no.6, pp.408-410, 2004.
10. D. Markovic et al., "Ultralow-power design in near-threshold region," Proc. of the IEEE, vol. 98, no. 2, pp. 237-252, 2010.
11. J. Black, "Electromigration - a brief survey and some recent results," IEEE T-ED, vol. 16, no. 4, pp. 338-347, 1969.
12. A. Sekiguchi, J. Koike, and K. Maruyama, "Microstructural influences on stress migration in electroplated Cu metallization," Appl. Phys. Lett., v ol. 83, no. 10, pp. 1962-1964, 2003.
13. J. Stathis, "Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits," IEEE T-DMR, vol. 1, no. 1, pp. 43-59, 2001.
14. J. Pang, D. Chong, and T. Low, "Thermal cycling analysis of flip-chip solder joint reliability," IEEE T-CPMT, vol. 24, no. 4, pp. 705-712, 2001.
15. K. Mistry et al., "A 45nm logic technology with high-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging," IEDM, pp. 247-250, 2007.
16. R. Havemann and J. Hutchby, "High-performance interconnects: an integration overview," Proc. of the IEEE, vol. 89, no. 5, pp. 586-601, 2001.
17. S. Bhardwaj et al., "Predictive modeling of the NBTI effect for reliable design," CICC pp. 189-192, 2006.
18. E. Takeda and N. Suzuki, "An empirical model for device degradation due to hot-carrier injection," IEEE EDL, vol. 4, no. 4, pp. 111-113, 1983.
19. P. Heremans et al., "Consistent model for the hot-carrier degradation in n-channel and p-channel MOSFETs," IEEE T-ED, vol. 35, no. 12, pp. 2194-2209, 1988.
20. J. Srinivasan et al., "The case for microarchitectural awareness of lifetime reliability," ISCA, 2004.
21. E. Y. Wu et al., "Interplay of voltage and temperature acceleration of oxide breakdown for ultra-thin gate dioxides," Solid-State Electronics Journal, 2002.
22. B. Gassend et al., "Silicon physical random functions," ACM CCS, pp. 148-160, 2002.
23. M. Majzoobi, F. Koushanfar, and M. Potkonjak, "Techniques for design and implementation of secure reconfigurable PUFs," ACM T-RETS, vol. 2, no. 1, pp. 1-33, 2009.
24. K. Gross, R. C. Dhankula, and A. J. Lewis, "Detecting counterfeit electronic components using EMI telemetric fingerprints." US Patent Application US 2009/009830 A1, 2009.
25. M. Agarwal et al., "Circuit failure prediction and its application to transistor aging," IEEE VTS, pp. 277-286, 2007.
26. N. Beckmann and M. Potkonjak, "Hardware-based public-key cryptography with public physically unclonable functions," IH, pp. 206-220, 2009.
27. M. Potkonjak, S. Meguerdichian, and A. Nahapetian, "Differential public physically unclonable functions: architecture and applications," DAC, pp. 242-247, 2011.
28. M. Tehranipoor and F. Koushanfar, "A survey of hardware Trojan taxonomy and detection," IEEE D & T of Computers, vol. 27, no. 1, pp. 10-25, 2010.
29. G. Qu and M. Potkonjak, "Intellectual Property Protection in VLSI Design," Kluwer Academic Publisher, 2003.
30. Technical report by U.S. Department Of Commerce, Bureau Of Industry And Security, Office Of Technology Evaluation, "Defense industrial base assessment: Counterfeit electronics," 2010.
31. U. Ruhrmair, S. Devadas, and F. Koushanfar, "Security based on Physical Unclonability and Disorder," Book Chapter in 'Introduction to Hardware Security and Trust', Editors: M. Tehranipoor and C. Wang, Springer, 2011.
32. F. Armknecht, R. Maes, A.-R. Sadeghi, F.-X. Standaert, and C. Wachsmann, "A formalization of the security features of physical functions," IEEE S & P, pp. 397-412, 2011.
33. T. Kim, R. Persaud, and C. H. Kim, "Silicon odometer: An on-chip reliability monitor for measuring frequency degradation of digital circuits," IEEE JSSC, vol. 43, no. 4, pp. 874-Ü880, 2008.
34. E. Karl et al., "Compact in-situ sensors for monitoring negative bias-temperature-instability effect and oxide degradation," ISSCC, pp. 410-411, 2008.
35. K.K. Kim, W. Wang, and K. Choi, "On-chip aging sensor circuits for reliable nanometer MOSFET digital circuits," T-CAS-II, vol.57, no. 10, pp.798-802, 2010.
36. F. Koushanfar, A-R. Sadeghi, and H. Seudie "EDA for Secure and Dependable Cybercars: Challenges and Opportunities," DAC, 2012.
37. M. Majzoobi and F. Koushanfar, "Time-Bounded Authentication of FPGAs," IEEEE T-IFS, v ol. 6 , no. 3, pp. 1123-1135 , 2011.
38. Analytical Solutions Inc., http://www.asinm.com/.
39. DARPA Microsystem Technology Office, http://www.darpa.mil/Our Work/MTO/.