VLSI testing based security metric for IC camouflaging

Proceedings - International Test Conference

Volumn , Issue , 2013, Pages

  Rajendran, Jeyavijayan ^a   Sinanoglu, Ozgur ^b   Karri, Ramesh ^a  

^a POLYTECHNIC UNIVERSITY   (United States)

^b NEW YORK UNIVERSITY ABU DHABI   (United Arab Emirates)

Author keywords

[No Author keywords available]

Indexed keywords

ABILITY TESTING; CELL ENGINEERING; REVERSE ENGINEERING; TIMING CIRCUITS; VLSI CIRCUITS;

NETLIST; SECURITY METRICES; STANDARD CELL; VLSI TESTING;

INTEGRATED CIRCUIT LAYOUT;

EID: 84891544717     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2013.6651879     Document Type: Conference Paper

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