HARPOON: An obfuscation-based SoC design methodology for hardware protection

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 28, Issue 1, 2009, Pages 1493-1502

  Chakraborty, Rajat Subhra ^a   Bhunia, Swarup ^a  

^a CASE WESTERN RESERVE UNIVERSITY   (United States)

Author keywords

Design for security; Hardware authentication; Hardware obfuscation; Intellectual property (IP) piracy; IP protection

Indexed keywords

BENCHMARK CIRCUIT; DELAY CONSTRAINTS; HARDWARE IP; HARDWARE PROTECTION; INTEGRAL PART; IP CORE; IP PROTECTION; IP VENDORS; MANUFACTURING FLOW; NETLIST; NOVEL DESIGN METHODOLOGY; POWER OVERHEAD; SECURITY HARDWARE; SIMULATION RESULT; SOC DESIGNS; SYSTEM ON CHIP DESIGN;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; AUTHENTICATION; CRIME; CRYPTOGRAPHY; DELAY CIRCUITS; DESIGN; MICROPROCESSOR CHIPS; NETWORK SECURITY; PROGRAMMABLE LOGIC CONTROLLERS;

HARDWARE;

EID: 77955216190     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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