Techniques for foundry identification

Proceedings - Design Automation Conference

Volumn , Issue , 2014, Pages

  Wendt, James B ^a   Koushanfar, Farinaz ^b   Potkonjak, Miodrag ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b Rice University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN;

CHANNEL LENGTH; EMPIRICAL DISTRIBUTIONS; IDENTIFICATION RATES; INTELLECTUAL PROPERTY PROTECTION; INTERVAL OF CONFIDENCE; KOLMOGOROV-SMIRNOV; RESUBSTITUTION; STATISTICAL TECHNIQUES;

FOUNDRIES;

EID: 84903196011     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2593069.2593228     Document Type: Conference Paper

References (26)

1. A. Asenov, A. R. Brown, J. H. Davies, S. Kaya, and G. Slavcheva, Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs, Trans. Electron Devices, vol. 50, no. 9, pp. 1837-1852, 2003.
2. N. Beckmann and M. Potkonjak, Hardware-based public-key cryptography with public physically unclonable functions, Information Hiding, pp. 206-220, 2009.
3. M. Potkonjak, S. Meguerdichian, A. Nahapetian, and S. Wei, Differential public physically unclonable functions: architecture and applications, DAC, pp. 242-247, 2011.
4. S. Meguerdichian and M. Potkonjak, Device aging-based physically unclonable functions, DAC, pp. 288-289, 2011.
5. J. B. Wendt and M. Potkonjak, Nanotechnology- based trusted remote sensing, IEEE Sensors, pp. 1213-1216, 2011.
6. J. B. Wendt and M. Potkonjak, The bidirectional polyomino partitioned PPUF as a hardware security primitive, GlobalSIP, pp. 257-260, 2013.
7. D. E. Holcomb, W. P. Burleson, and K. Fu, Power-up SRAM state as an identifying fingerprint and source of true random numbers, Trans. Computers, vol. 58, no. 9, pp. 1198-1210, 2009.
8. F. Koushanfar and G. Qu, Hardware metering, DAC, pp. 490-493, 2001.
9. Y. Alkabani and F. Koushanfar, Active hardware metering for intellectual property protection and security, USENIX Security, pp. 291-306, 2007.
10. S. Wei, S. Meguerdichian, and M. Potkonjak, Gate-level characterization: foundations and hardware security applications, DAC, pp. 222-227, 2010.
11. M. Potkonjak, A. Nahapetian, M. Nelson, and T. Massey, Hardware Trojan horse detection using gate-level characterization, DAC, pp. 688-693, 2009.
12. J. S. J. Wong, P. Sedcole, and P. Y. K. Cheung, Self-measurement of combinatorial circuit delays in FPGAs, TRETS, vol. 2, no. 2, pp. 1-22, 2009.
13. Y. Alkabani, F. Koushanfar, N. Kiyavash, and M. Potkonjak, Trusted integrated circuits: a nondestructive hidden characteristics extraction approach, Information Hiding, pp. 102-117, 2008.
14. S. Wei and M. Potkonjak, Scalable hardware Trojan diagnosis, Trans. VLSI, vol. 20, no. 6, pp. 1049-1057, 2012.
15. Y. Alkabani, T. Massey, F. Koushanfar, and M. Potkonjak, Input vector control for post-silicon leakage current minimization in the presence of manufacturing variability, DAC, pp. 606-609, 2008.
16. B. Cline, K. Chopra, D. Blaauw, and Y. Cao, Analysis and modeling of CD variation for statistical static timing, ICCAD, pp. 60-66, 2006.
17. S. Nassif et al., High performance CMOS variability in the 65nm regime and beyond, IEDM, pp. 569-571, 2007
18. K. Agarwal and S. Nassif, Characterizing process variation in nanometer CMOS, DAC, pp. 396-399, 2007.
19. K. J. Kuhn, Reducing variation in advanced logic technologies: approaches to process and design for manufacturability of nanoscale CMOS, IEDM, pp. 471-474, 2007.
20. D. E. Knuth, The Art of Computer Programming: Sorting and Searching, vol. 3, Addison-Wesley Professional, 1998.
21. D. Markovi'c, C. C. Wang, L. P. Alarc'on, T.-T. Liu, and J. M. Rabaey, Ultralow-power design in near-threshold region, Proceedings of the IEEE, vol. 98, no. 2, pp. 237-252, 2010.
22. F. Brglez, A neutral netlist of 10 combinational benchmark circuits and a target translation in FORTRAN, ISCAS, 1985.
23. S. Wei, A. Nahapetian, M. Potkonjak, Robust passive hardware metering, ICCAD, pp. 802-809, 2010.
24. S. Chakravarthi, A. Krishnan, V. Reddy, C. F. Machala, and S. Krishnan. A comprehensive framework for predictive modeling of negative bias temperature instability, IRPS, pp. 273- 282, 2004.
25. F. Brglez, D. Bryan, and K. Kozminski, Combinational profiles of sequential benchmark circuits, ISCAS, pp. 1929-1934, 1989.
26. F. Corno, M. S. Reorda, and G. Squillero, RT-level ITC'99 benchmarks and first ATPG results, IEEE Design and Test of Computers, vol. 17, no. 3, pp. 44-53, 2000.