Security analysis of logic obfuscation

Proceedings - Design Automation Conference

Volumn , Issue , 2012, Pages 83-89

  Rajendran, Jeyavijayan ^a   Pino, Youngok ^b   Sinanoglu, Ozgur ^c   Karri, Ramesh ^a  

^a NEW YORK UNIVERSITY   (United States)

^b AIR FORCE RESEARCH LABORATORY   (United States)

^c NEW YORK UNIVERSITY ABU DHABI   (United Arab Emirates)

Author keywords

IP protection; logic obfuscation

Indexed keywords

COMPUTER AIDED DESIGN; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUITS; SUPPLY CHAINS;

DESIGN FLOWS; IP PROTECTION; KEY VALUES; LOGIC OBFUSCATION; NETLIST; SECURITY ANALYSIS;

COMPUTER CIRCUITS;

EID: 84863542083     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2228360.2228377     Document Type: Conference Paper

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