메뉴 건너뛰기




Volumn 9, Issue 3, 2013, Pages

Design space exploration of FinFET cache

Author keywords

Cache; FinFETs; Power consumption; SRAM

Indexed keywords

CACHE; COOLING TECHNOLOGY; DESIGN SPACE EXPLORATION; FINFETS; HIGH-PERFORMANCE COMPUTING; LEAKAGE REDUCTION TECHNIQUES; POWER-DELAY PRODUCTS; PROCESSOR DESIGNERS;

EID: 84885613489     PISSN: 15504832     EISSN: 15504840     Source Type: Journal    
DOI: 10.1145/2491678     Document Type: Article
Times cited : (5)

References (39)
  • 1
    • 79955561467 scopus 로고    scopus 로고
    • Comparative evaluation of layout density in 3T, 4T, and MT FinFET standard cells
    • ALIOTO, M. 2011. Comparative evaluation of layout density in 3T, 4T, and MT FinFET standard cells. IEEE Trans. VLSI Syst. 19, 751-762.
    • (2011) IEEE Trans. VLSI Syst. , vol.19 , pp. 751-762
    • Alioto, M.1
  • 2
    • 34547234742 scopus 로고    scopus 로고
    • A fully physical model for leakage distribution under process variations in nanoscale double-gate CMOS
    • ANANTHAN, H. AND ROY, K. 2006. A fully physical model for leakage distribution under process variations in nanoscale double-gate CMOS. In Proceedings of the Design Automation Conference (DAC'06). 413-419.
    • (2006) Proceedings of the Design Automation Conference (DAC'06) , pp. 413-419
    • Ananthan, H.1    Roy, K.2
  • 3
    • 78650644644 scopus 로고    scopus 로고
    • Gated-diode FinFET DRAMs: Device and circuit design considerations
    • BHOJ, A. N. AND JHA, N. K. 2010. Gated-diode FinFET DRAMs: Device and circuit design considerations. ACM J. Emerg. Technol. Comput. Syst. 6, 4.
    • (2010) ACM J. Emerg. Technol. Comput. Syst. , vol.6 , pp. 4
    • Bhoj, A.N.1    Jha, N.K.2
  • 9
    • 51949118050 scopus 로고    scopus 로고
    • Modeling and circuit synthesis for independently controlled double gate FinFET devices
    • DATTA, A., GOEL, A., CAKICI, R. T., MAHMOODI, H., LAKSHMANAN, D., AND ROY, K. 2007. Modeling and circuit synthesis for independently controlled double gate FinFET devices. IEEE Trans. Comput.-Aid. Des. 26, 11, 1957-1966.
    • (2007) IEEE Trans. Comput.-Aid. Des. , vol.26 , Issue.11 , pp. 1957-1966
    • Datta, A.1    Goel, A.2    Cakici, R.T.3    Mahmoodi, H.4    Lakshmanan, D.5    Roy, K.6
  • 13
    • 38349114770 scopus 로고    scopus 로고
    • Statistical leakage estimation of double gate FinFET devices considering the width quantization property
    • GU, J., KEANE, J., SAPATNEKAR, S., AND KIM, C. H. 2008. Statistical leakage estimation of double gate FinFET devices considering the width quantization property. IEEE Trans. VLSI Syst. 16, 206-209.
    • (2008) IEEE Trans. VLSI Syst. , vol.16 , pp. 206-209
    • Gu, J.1    Keane, J.2    Sapatnekar, S.3    Kim, C.H.4
  • 17
    • 0345757132 scopus 로고    scopus 로고
    • Let caches decay: Reducing leakage energy via exploitation of cache generational behavior
    • HU, Z., KAXIRAS, S., AND MARTONOSI, M. 2002. Let caches decay: Reducing leakage energy via exploitation of cache generational behavior. ACM Trans. Comput. Syst. 20, 161-190.
    • (2002) ACM Trans. Comput. Syst. , vol.20 , pp. 161-190
    • Hu, Z.1    Kaxiras, S.2    Martonosi, M.3
  • 21
    • 77951014489 scopus 로고    scopus 로고
    • FinFET-based dynamic power management of on-chip interconnection networks through adaptive back-gate biasing
    • LEE, C.-Y. AND JHA, N. K. 2009. FinFET-based dynamic power management of on-chip interconnection networks through adaptive back-gate biasing. In Proceedings of the International Conference on Computer Design.
    • (2009) Proceedings of the International Conference on Computer Design
    • Lee, C.-Y.1    Jha, N.K.2
  • 22
    • 80052672058 scopus 로고    scopus 로고
    • CACTI-FinFET: An integrated delay and power modeling framework for FinFET-based caches under process variations
    • LEE, C.-Y. AND JHA, N. K. 2011. CACTI-FinFET: An integrated delay and power modeling framework for FinFET-based caches under process variations. In Proceedings of the Design Automation Conference (DAC). 866-871.
    • (2011) Proceedings of the Design Automation Conference (DAC) , pp. 866-871
    • Lee, C.-Y.1    Jha, N.K.2
  • 23
    • 16244376777 scopus 로고    scopus 로고
    • High performance and low power domino logic using independent gate control in double-gate SOI MOSFETs
    • MAHMOODI, H.,MUKHOPADHYAY, S., AND ROY, K. 2004. High performance and low power domino logic using independent gate control in double-gate SOI MOSFETs. In Proceedings of the International SOI Conference. 67-68.
    • (2004) Proceedings of the International SOI Conference , pp. 67-68
    • Mahmoodi, H.1    Mukhopadhyay, S.2    Roy, K.3
  • 34
    • 51849099498 scopus 로고    scopus 로고
    • High speed FinFET domino logic circuits using independent gatebiased double-gate keepers providing dynamically adjusted immunity to noise
    • TAWFIK, S. A. AND KURSUN, V. 2007a. High speed FinFET domino logic circuits using independent gatebiased double-gate keepers providing dynamically adjusted immunity to noise. In Proceedings of the International Conference on Microelectronics. 175-178.
    • (2007) Proceedings of the International Conference on Microelectronics , pp. 175-178
    • Tawfik, S.A.1    Kursun, V.2
  • 37
    • 0030149507 scopus 로고    scopus 로고
    • CACTI: An enhanced cache access and cycle time model
    • WILTON, S. J. E. AND JOUPPI, N. P. 1996. CACTI: An enhanced cache access and cycle time model. IEEE J. Solid-State Circ. 31, 5, 677-688.
    • (1996) IEEE J. Solid-State Circ. , vol.31 , Issue.5 , pp. 677-688
    • Wilton, S.J.E.1    Jouppi, N.P.2
  • 38
    • 0242332710 scopus 로고    scopus 로고
    • Sensitivity of double-gate and FinFET devices to process variations
    • XIONG, S. AND BOKOR, J. 2003. Sensitivity of double-gate and FinFET devices to process variations. IEEE Trans. Electron. Dev. 50, 2255-2261.
    • (2003) IEEE Trans. Electron. Dev. , vol.50 , pp. 2255-2261
    • Xiong, S.1    Bokor, J.2
  • 39
    • 33846192734 scopus 로고    scopus 로고
    • ISAC: Integrated space-and-time-adaptive chippackage thermal analysis
    • YANG, Y., GU, Z., ZHU, C., DICK, R. P., AND SHANG, L. 2007. ISAC: Integrated space-and-time-adaptive chippackage thermal analysis. IEEE Trans. Comput.-Aid. Des. 26, 1, 86-99.
    • (2007) IEEE Trans. Comput.-Aid. Des. , vol.26 , Issue.1 , pp. 86-99
    • Yang, Y.1    Gu, Z.2    Zhu, C.3    Dick, R.P.4    Shang, L.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.