High performance and low power domino logic using independent gate control in double-gate SOI MOSFETs

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2004, Pages 67-68

  Mahmoodi, Hamid ^a   Mukhopadhyay, Saibal ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DOMINO LOGIC; DOUBLE-GATE SOI MOSFET (DGMOS); PARALLEL TRANSISTORS; POWER DISSIPATION;

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC INVERTERS; ELECTRIC NETWORK ANALYSIS; ELECTRIC POTENTIAL; GATES (TRANSISTOR); SILICON ON INSULATOR TECHNOLOGY; TOPOLOGY;

MOSFET DEVICES;

EID: 16244376777     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. L. Chang, et. al., "Extremely Scaled Silicon Nano-CMOS Devices," Proceedings of the IEEE, Vol. 91, Issue: 11, pp. 1860-1873, Nov. 2003
2. Design of High-Performance Microprocessor Circuits, A. Chandrakasan, W.J. Bowhill, and F. Fox, Piscataway, NJ, USA: IEEE Press, 2001.