CACTI-FinFET: An integrated delay and power modeling framework for FinFET-based caches under process variations

Proceedings - Design Automation Conference

Volumn , Issue , 2011, Pages 866-871

  Lee, Chun Yi ^a   Jha, Niraj K ^a  

^a Princeton University   (United States)

Author keywords

cache simulator; CACTI FinFET; FinFETs; process variation

Indexed keywords

CACHE SIMULATORS; CACTI-FINFET; DESIGN LIBRARY; DESIGN STYLES; FINFETS; INTEGRATED FRAMEWORKS; POWER MODELING; PROCESS VARIATION;

COMPUTER AIDED DESIGN;

INTEGRATED CIRCUITS;

EID: 80052672058     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

1. A. Agarwal, D. Blaauw, and V. Zolotov. Statistical timing analysis for intra-die process variations with spatial correlations. In Proc. Int. Conf. Computer-Aided Design, pages 900-907, 2003.
2. S. Borkar et al. Parameter variations and impact on circuits and microarchitecture. In Proc. Design Automation Conf., pages 338-342, 2003.
3. A. Carlson et al. FinFET SRAM with enhanced read/write margins. In Proc. Int. SOI Conf., pages 105-106, 2006.
4. H. Chang and S. Sapatnekar. Statistical timing analysis under spatial correlations. IEEE Trans. Computer-Aided Design, 24(9):1467-1482, 2005. (Pubitemid 41558372)
5. J. H. Choi, J. Murthy, and K. Roy. The effect of process variation on device temperature in FinFET circuits. In Proc. Int. Conf. Computer-Aided Design, pages 747-751, 2007.
6. J. G. Fossum et al. A process/physics-based compact model for nonclassical CMOS device and circuit design. Solid State Electronics, 48(6):919-926, 2004.
7. S. Ganapathy, R. Canal, A. Gonzalez, and A. Rubio. Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability. In Proc. Design, Automation & Test in Europe Conf., pages 417-422, 2010.
8. Z. Guo, S. Balasubramanian, R. Zlatanovici, T.-J. King, and B. Nikolic. FinFET-based SRAM design. In Proc. Int. Symp. Low Power Electronics and Design, pages 2-7, 2005.
9. R. Joshi, K. Kim, R. Williams, E. Nowak, and C.-T. Chuang. A high-performance, low leakage, and stable SRAM row-based back-gate biasing scheme in FinFET technology. In Proc. Int. Conf. VLSI Design, pages 665-672, 2007.
10. S.-Y. Kim et al. Temperature dependence of substrate and drain currents in bulk FinFETs. IEEE Trans. Electron Devices, 54(5):1259-1264, May 2007. (Pubitemid 46691580)
11. Y. B. Kim, Y.-B. Kim, and F. Lombardi. Low power 8T SRAM using 32nm independent gate FinFET technology. In Proc. Int. SOC Conf., pages 247-250, 2008.
12. S. Li et al. McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures. In Proc. Int. Symp. Microarchitecture, pages 469-480, 2009.
13. P. Mishra, A. Bhoj, and N. K. Jha. Die-level leakage power analysis of FinFET circuits considering process variations. In Proc. Int. Symp. Quality Electronic Design, pages 347-355, 2010.
14. A. Muttreja, N. Agarwal, and N. K. Jha. CMOS logic design with independent-gate FinFETs. In Proc. IEEE Int. Conf. Computer Design, pages 560-567, 2007.
15. S. Rasouli, K. Endo, and K. Banerjee. Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantization. In Proc. IEEE/ACM Int. Conf. Computer-Aided Design, pages 505-512, 2009.
16. A. Singhee and R. A. Rutenbar. From finance to flip flops: A study of fast quasi-Monte Carlo methods from computational finance applied to statistical circuit analysis. In Proc. Int. Symp. Quality of Electronic Design, pages 685-692, 2007.
17. R. Thakker et al. A novel table-based approach for design of FinFET circuits. IEEE Trans. Computer-Aided Design, 28(7):1061-1070, 2009.