Power optimization for FinFET-based circuits using genetic algorithms

2008 IEEE International SOC Conference, SOCC

Volumn , Issue , 2008, Pages 211-214

  Ouyang, Jin ^a   Yuanxie, ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

32 NM TECHNOLOGY; BULK CMOS; CIRCUIT DESIGNERS; CIRCUIT DESIGNS; DESIGN GOAL; FINFET DEVICES; GATE SIZING; LOW POWER TECHNIQUES; PERFORMANCE CONSTRAINTS; POWER CONSUMPTION; POWER OPTIMIZATION; POWER REDUCTIONS; REDUCING POWER; UNIQUE FEATURES;

DESIGN; ELECTRIC POWER UTILIZATION; FIELD EFFECT TRANSISTORS; GATES (TRANSISTOR); OPTIMIZATION;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 67650224990     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCC.2008.4641513     Document Type: Conference Paper

References (10)

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