Comparative evaluation of layout density in 3T, 4T, and MT FinFET standard cells

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 19, Issue 5, 2011, Pages 751-762

  Alioto, Massimo ^a,b  

^a UNIVERSITY OF SIENA   (Italy)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Digital circuits; FinFET; layout density; nanometer CMOS; physical design; standard cell; VLSI

Indexed keywords

FINFET; LAYOUT DENSITY; NANOMETER CMOS; PHYSICAL DESIGN; STANDARD CELL; VLSI;

CYTOLOGY; DESIGN; DIGITAL INTEGRATED CIRCUITS; ELECTRIC BATTERIES; FINS (HEAT EXCHANGE); GATES (TRANSISTOR); INTEGRATED CIRCUITS; LIBRARIES; STANDARDS; VLSI CIRCUITS;

CELLS;

EID: 79955561467     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2010.2040094     Document Type: Article

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