FinFET-based Dynamic Power Management of On-chip Interconnection Networks through Adaptive Back-gate Biasing

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2009, Pages 350-357

  Lee, Chun Yi ^a   Jha, Niraj K ^a  

^a Princeton University   (United States)

Author keywords

FinFETs; GARNET; Interconnection network; ORION; Voltage generator; VPSR

Indexed keywords

32-NM NODE; BACK-GATE BIASING; BULK CMOS; CHIP MULTIPROCESSOR; DETAILED DESIGN; DYNAMIC POWER MANAGEMENT; FINFETS; IC PACKAGE; INCOMING TRAFFIC; LEAKAGE POWER; NANO-METER REGIMES; ON-CHIP INTERCONNECTION NETWORK; ON-CHIP NETWORKS; PERFORMANCE SIMULATION; POWER CONSUMPTION; SHORT-CHANNEL EFFECT; SIMULATION PLATFORM; SYSTEM RELIABILITY; VOLTAGE GENERATORS;

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DESIGN; ELECTRIC POWER MEASUREMENT; ENERGY MANAGEMENT; GARNETS; INTERCONNECTION NETWORKS; SILICATE MINERALS;

ROUTERS;

EID: 77951014489     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2009.5413133     Document Type: Conference Paper

References (23)

1. M. B. Taylor et al., "Evaluation of the Raw microprocessor: An exposed-wire-delay architecture for ILP and streams," in Proc. Int. Symp. Computer Architecture, pp. 2-1.3, Jun. 2004.
2. K. Sankaralingam et al., "Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture," in Proc. Int. Symp. Computer Architecture., pp. 422-433, Jun. 2003.
3. K. Mai, T. Paaske, N. Jayasena, R. Ho, W. Dally, and M. Horowitz, "Smart memories: A modular reconfigurable architecture," in Proc. Int. Symp. Computer Architecture, pp. 161-171, Jun. 2000.
4. D. C. Pham et al., "Overview of the architecture, circuit designs and physical implementation of the first generation cell processor," IEEE J. Solid-State Circuits, vol.41, no.1, pp. 179-196, Jan. 2006.
5. Y. Hoskote et al., "A 5-GHz mesh interconnect for a teraflops processor," IEEE Micro, vol.27, no.5, pp. 51-61, Sep.-Oct. 2007.
6. J. S. Kim, M. B. Taylor, J. Miller, and. D. Wentzlaff, "Energy characterization of a tiled architecture processor with on-chip networks," in Proc. Int. Symp. Low Power Electronics and Design, pp. 424-427, Aug. 2003.
7. L. Shang, L.-S. Peh, and N. K. Jha, "PowerHerd: A distributed scheme for dynamically satisfying peak-power constraints in interconnection, networks," IEEE Trans. Computer-Aided Design, vol.25, no.1 pp. 92-110, Jan. 2006.
8. L. Shang, L.-S. Peh, and N. K. Jha, "Dynamic voltage scaling with links for power optimization of interconnection networks," in Proc. Int. Symp. High-Performance Computer Architecture, pp. 91-102, Feb. 2003.
9. J. Kao, S. Narendra, and A. Chandrakasan, "Subthreshold leakage modeling and reduction techniques," in Proc. Int. Conf. ComputerAided Design, pp. 141-148, Nov. 2002.
10. A. Muttreja, P. Mishra, and N. K. Jha, "Threshold voltage control through multiple supply voltages for power-efficient FinFET interconnects," in Proc. Int. Conf. VLSI Design, pp. 220-227, Jan. 2008.
11. "International Technology Roadmap for Semiconductors," http://www.itrs.net.
12. R. V. Joshi, K. Kim, R. Q. Williams, E. J. Nowak, and C.-T. Chuang, "A high-performance, low leakage, and stable SRAM row-based backgate biasing scheme in FinFET technology," in Proc. Intl. Conf. VLSI Design, pp. 665-672, Jan. 2007.
13. B. Swahn and S. Hassoun, "Gate sizing: FinFET vs. 32nm bulk MOSFETs," in Proc. Design Automation Conf., pp. 528-531, Jul. 2006.
14. A. Muttreja, N. Agarwal, and N. K. Jha, "CMOS logic design with independent-gate FinFETs," in Proc. Int. Conf. Computer Design, pp. 560-567, Oct. 2007.
15. C.-Y. Lee and N. K. Jha, "FinFET-based power simulator for interconnection networks," submitted to ACM J. Emerging Technologies in Computing Systems.
16. N. K. Jha, "Low power system scheduling and synthesis," in Proc. Int. Conf. Computer-Aided Design, pp. 259-263, Nov. 2001.
17. J. Tschanz et al., "Adaptive body bias for reducing impacts of die-todie and within-die parameter variations on microprocessor frequency and leakage," IEEE J. Solid-State Circuits, vol.37, no.11, pp. 1396-1402, Nov. 2002.
18. J. K. Ousterhout, G. T. Hamachi, R. N. Mayo, W. S. Scott, and G. S. Taylor, "MAGIC: A VLSI layout system," in Proc. Design Automation Conf., pp. 152-159, Jun. 1984.
19. T.-J. King, "FinFETs for nanoscale CMOS digital integrated circuits," in Proc. Int. Conf. Computer-Aided Design, pp. 207-210, Nov. 2005.
20. N. Agarwal, T. Krishna, L.-S. Peh, and N. K. Jha, "GARNET: A detailed interconnection network model inside a fullsystem simulator," in Proc. Int. Symp. Performance Analysis of Systems and Software, Apr. 2009. Available for download from: http://www.cs.wisc.edu/gems/download.html.
21. H. Wang, X. Zhu, L.-S. Peh, and S. Malik, "ORION: A powerperformance simulator for interconnection networks," in Proc. Int. Symp. Microarchitecture, pp. 294-305, Nov. 2002.
22. J. G. Fossum. et al., "A process/physics-based compact model for nonclassical CMOS device and circuit design," Solid State Electronics, vol.48, no.6, pp. 919-926, Jun. 2004.
23. L. Shang, L.-S. Peh, A. Kumar, and N. K. Jha, "Temperature-aware on-chip networks," IEEE Micro, vol.26, no.1, pp. 130-139, Jan.-Feb. 2006.