A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 413-418

  Ananthan, Hari ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

Double gate; FinFET; Leakage distribution; Multiple gate; Process variations; Tri gate

Indexed keywords

CMOS INTEGRATED CIRCUITS; LOGIC GATES; NONLINEAR EQUATIONS; QUANTUM THEORY; SILICON ON INSULATOR TECHNOLOGY;

DOUBLE-GATES; LEAKAGE DISTRIBUTION; MULTIPLE-GATE; PROCESS VARIATIONS; TRI-GATE;

LEAKAGE CURRENTS;

EID: 34547234742     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1147020     Document Type: Conference Paper

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