-
1
-
-
29144494605
-
On-chip thermal gradient analysis and temperature flattening for SoC design
-
December
-
T. Sato et al., "On-chip thermal gradient analysis and temperature flattening for SoC design," IEICE Trans. Fundamentals, vol. E88-A, no. 12, pp. 3382-3389. December 2005.
-
(2005)
IEICE Trans. Fundamentals
, vol.E88-A
, Issue.12
, pp. 3382-3389
-
-
Sato, T.1
-
3
-
-
1842865629
-
Turning silicon on its edge [Double gate CMOS/FinFET technology]
-
January-Febrary
-
E. Nowak et al., "Turning silicon on its edge [Double gate CMOS/FinFET technology]," IEEE Trans. Circuits Devices Mag., pp. 20-31, January-Febrary 2004.
-
(2004)
IEEE Trans. Circuits Devices Mag
, pp. 20-31
-
-
Nowak, E.1
-
4
-
-
0842309721
-
Thermal analysis of ultra-thin body device scaling
-
December
-
E. Pop et al., "Thermal analysis of ultra-thin body device scaling." in IEDM 2003, December 2003, pp. 883-886.
-
(2003)
IEDM 2003
, pp. 883-886
-
-
Pop, E.1
-
5
-
-
0242332710
-
Sensitivity of double-gate and FinFET devices to process variations
-
November
-
S. Xiong and J. Bokor, "Sensitivity of double-gate and FinFET devices to process variations," IEEE Trans. Election Devices, vol. 50, no. 11, pp. 2255-2261, November 2003.
-
(2003)
IEEE Trans. Election Devices
, vol.50
, Issue.11
, pp. 2255-2261
-
-
Xiong, S.1
Bokor, J.2
-
6
-
-
27944470947
-
Full-chip analysis of leakage power under process variations, including spatial correlations
-
June
-
H. Chang and S. S. Sapatnekar, "Full-chip analysis of leakage power under process variations, including spatial correlations," in Proc. of DAC 2005, June 2005, pp. 523-528.
-
(2005)
Proc. of DAC 2005
, pp. 523-528
-
-
Chang, H.1
Sapatnekar, S.S.2
-
7
-
-
1542269365
-
Statistical estimation of leakage current considering inter-and intra-die process variation
-
August
-
R. Rao et al., "Statistical estimation of leakage current considering inter-and intra-die process variation," in Proc. of ISLPED 2003, August 2003, pp. 84-89.
-
(2003)
Proc. of ISLPED 2003
, pp. 84-89
-
-
Rao, R.1
-
10
-
-
33748323313
-
Modeling and analysis of leakage currents in double-gate technologies
-
October
-
S. Mukhopadhyay et al., "Modeling and analysis of leakage currents in double-gate technologies," IEEE Trans. CAD. vol. 25, no. 10, pp. 2052-2061, October 2006.
-
(2006)
IEEE Trans. CAD
, vol.25
, Issue.10
, pp. 2052-2061
-
-
Mukhopadhyay, S.1
-
11
-
-
50249114073
-
-
Taurus device simulator, Synopsys Inc
-
Taurus device simulator, Synopsys Inc.
-
-
-
-
12
-
-
0033169528
-
A compact double-gate MOSFET model comprising quantum-mechanical and nonstatic effects
-
August
-
G. Baccarani and S. Reggiani, "A compact double-gate MOSFET model comprising quantum-mechanical and nonstatic effects." IEEE Trans. Electron Devices, vol. 46, no. 8, pp. 1656-1666, August 1999.
-
(1999)
IEEE Trans. Electron Devices
, vol.46
, Issue.8
, pp. 1656-1666
-
-
Baccarani, G.1
Reggiani, S.2
-
13
-
-
0348040085
-
Statistical timing analysis for intra-die process variations with spatial correlations
-
November
-
A. Agarwal et al., "Statistical timing analysis for intra-die process variations with spatial correlations," in Proc. of ICCAD 2003. November 2003, pp. 900-907.
-
(2003)
Proc. of ICCAD 2003
, pp. 900-907
-
-
Agarwal, A.1
-
14
-
-
37749001321
-
Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits
-
November
-
J. Choi et al., "Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits," in Proc. of ICCAD 2006, November 2006, pp. 583-586.
-
(2006)
Proc. of ICCAD 2006
, pp. 583-586
-
-
Choi, J.1
-
15
-
-
50249110676
-
-
Fluent CFD software. ANSYS Inc
-
Fluent CFD software. ANSYS Inc.
-
-
-
|