Gate sizing: FinFETs vs 32nm bulk MOSFETs

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 528-531

  Swahn, Brian ^a   Hassoun, Soha ^a  

^a TUFTS UNIVERSITY   (United States)

Author keywords

FinFET; Gate sizing; Thermal modeling

Indexed keywords

CIRCUIT SIMULATION; CONSTRAINT THEORY; ELECTRIC CURRENT CONTROL; LOGIC DESIGN; MOSFET DEVICES; PROGRAMMABLE LOGIC CONTROLLERS;

FINFET; GATE SIZING; THERMAL MODELING;

GATES (TRANSISTOR);

EID: 34249795033     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1147047     Document Type: Conference Paper

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