CMOS logic design with independent-gate FinFETs

2007 IEEE International Conference on Computer Design, ICCD 2007

Volumn , Issue , 2007, Pages 560-567

  Muttreja, Anish ^a   Agarwal, Niket ^a   Jha, Niraj K ^a  

^a Princeton University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE LEAKAGE; BULK CMOS; CMOS LOGIC; COMPUTER DESIGNS; DELAY CONSTRAINTS; DESIGN STYLES; FINFETS; INDEPENDENT CONTROL; INTERNATIONAL CONFERENCES; NANO SCALING; POWER SAVINGS; TOTAL POWER CONSUMPTION;

ENERGY CONSERVATION; FIELD EFFECT TRANSISTORS; LOGIC DESIGN; SWITCHING CIRCUITS; SWITCHING THEORY; TRANSISTORS;

LOGIC CIRCUITS;

EID: 47649083623     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2007.4601953     Document Type: Conference Paper

References (26)

1. E. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong. Device scaling limits of Si MOSFETs and their application dependencies. Proc. IEEE, 89(3):259-288, Mar. 2001.
2. 2005 International Technology Roadmap for Semiconductors. http://www.itrs.net/.
3. T.-J. King. FinFETs for nanoscale CMOS digital integrated circuits. In Proc. Int. Conf. Computer-Aided Design, pages 207-210, Nov. 2005.
4. L. Wei, Z. Chen, and K. Roy. Double gate dynamic threshold voltage (DGDT) SOI MOSFETs for low power high performance designs. In Proc. IEEE Int. SOI Conf., pages 82-83, Oct. 1997.
5. P. Beckett. A fine-grained reconfigurable logic array based on double gate transistors. In Proc. IEEE Int. Field-Programmable Technology Conf., pages 260-267, Dec. 2002.
6. I. Aller. The double-gate FinFET: Device impact on circuit design. In Proc. Int. Solid-State Circuits Conf., pages 14-15 (and visual supplements, pp. 655-657), Feb. 2003.
7. I. Yang, A. Chandrakasan, and D. Antoniadis. Backgated CMOS on SOIAS for dynamic threshold voltage control. IEEE Trans. Electron Devices, 44(5):822-831, May 1997.
8. E. J. Nowak, I. Aller, T. Ludwig, K. Kim, R. V. Joshi, C.-T. Chuang, K. Bernstein, and R. Puri. Turning silicon on its edge. IEEE Circuits and Devices Magazine, 20(1):20-31, Jan.-Feb. 2004.
9. B. Swahn and S. Hassoun. Gate sizing: FinFETs vs 32nm bulk MOSFETs. In Proc. ACM/IEEE Design Automation Conf., pages 528-531, July 2006.
10. J. Kao, S. Narendra, and A. Chandrakasan. Subthreshold leakage modeling and reduction techniques. In Proc. Int. Conf. Computer-Aided Design, pages 141-148, Nov. 2002.
11. th assignment. In Proc. Int. Symp. Low Power Electronics & Design, pages 149-154, Aug. 2005.
12. L. Mathew et al. CMOS vertical multiple independent gate field effect transistor (MIGFET). In Proc. IEEE Int. SOI Conf., pages 187-189, Oct. 2004.
13. D. M. Fried, E. J. Nowak, J. Kedzierski, J. S. Duster, and K. T. Kornegay. A fin-type independent double-gate NFET. In Proc. Device Research Conf., pages 45-46, June 2003.
14. M.-H. Chiang, K. Kim, C. Tretz, and C.-T. Chuang. Novel high-density low-power logic circuit techniques using DG devices. IEEE Electronic Device Lett., 52(10):2339-2342, Oct. 2005.
15. H. Mahmoodi, S. Mukhopadhyay, and K. Roy. High performance and low power domino logic using independent gate control in double-gate SOI MOSFETs. In Proc. IEEE Int. SOI Conf., pages 67-68, Oct. 2004.
16. W. Zhang, J. G. Fossum, L. Mathew, and Y. Du. Physical insights regarding design and performance of independent-gate FinFETs. IEEE Electronic Device Lett., 52(10):2189-2206, Oct. 2005.
17. P. Beckett. Low-power circuits using dynamic threshold voltage devices. In Proc. Great Lakes Symp. VLSI, pages 213-216, Apr. 2005.
18. T. Cakici, H. Mahmoodi, S. Mukhopadhyay, and K. Roy. Independent gate skewed logic in double-gate SOI technology. In Proc. IEEE Int. SOI Conf., pages 83-84, Oct. 2005.
19. R. V. Joshi, K. Kim, R. Q. Williams, E. J. Nowak, and C.-T. Chuang. A high-performance, low leakage, and stable SRAM row-based back-gate biasing scheme in FinFET technology. In Proc. Int. Conf. VLSI Design, pages 665-672, Jan. 2007.
20. D. Nguyen, A. Davare, M. Orshansky, D. Chinnery, B. Thompson, and K. Keutzer. Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization. In Proc. Int. Symp. Low Power Electronics & Design, pages 158-163, Aug. 2003.
21. W. Zhao and Y. Cao. New generation of predictive technology model for sub-45nm design exploration. In Proc. Int. Symp. Quality of Electronic Design, pages 585-590, May 2006. http://www.eas.asu.edu/~ptm.
22. W. Zhao and Y. Cao. Predictive technology model for nano-CMOS design exploration. ACM J. Emerging Technologies in Computing Systems, 3(1):1-17, Apr. 2007.
23. J. H. Choi, A. Bansal, M. Meterelliyoz, J. Murthy, and K. Roy. Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits. In Proc. Int. Conf. Computer-Aided Design, pages 583-586, Nov. 2006.
24. I. Sutherland, R. F. Sproull, and D. Harris. Logical Effort: Designing Fast CMOS Circuits. Morgan Kaufmann, San Fransisco, CA, 1999.
25. G. Petley. VLSI and ASIC technology standard cell, library design, http://vlsitechnology.org.
26. D. Sylvester and K. Keutzer. Getting to the bottom of deep submicron. In Proc. Int. Conf. Computer-Aided Design, pages 203-211, Nov. 1998.