Low power 8T SRAM using 32nm independent gate FinFET technology

2008 IEEE International SOC Conference, SOCC

Volumn , Issue , 2008, Pages 247-250

  Young, Bok Kim ^a   Kim, Yong Bin ^a   Lombardi, Fabrizio ^a  

^a Northeastern University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

6T-SRAM; BACK GATES; DYNAMIC POWER; DYNAMIC POWER CONSUMPTION; LEAKAGE POWER; LOW POWER; POWER CONSUMPTION; SRAM CELL; STATIC NOISE MARGIN;

CELL MEMBRANES; ELECTRIC POTENTIAL; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRIC POWER UTILIZATION; FIELD EFFECT TRANSISTORS;

STATIC RANDOM ACCESS STORAGE;

EID: 67650242700     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCC.2008.4641521     Document Type: Conference Paper

References (6)

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2. R.V. Joshi, R.Q. Williams, E. Nowak, K. Kim, J.Beintner, T. Ludwig, I. Aller, and C. Chuang,"FinFET SRAM for high-performance low-power applications", Proceeding of the 34th European Solid-State Device Research conference, pp. 69 - 72, 2004
3. X. Huang, et al., "Sub-50 nm P-channgel FinFET," IEEE TED, vol. 48, pp. 880-886, 2001
4. "Predictive Technology Model for 32 nm CMOS FinFET echnologies", http://www.eas.asu.edu/~ptm/
5. Sherif A. Tawfik Volkan Kursun, "Low-Power and Compact Sequential Circuits With Independent-Gate FinFETs" , IEEE Transactions on Electron Devices, Vol. 55, no. 1, January 2008
6. A. Bhavnaganwala, X. Tang, and J. D. Meindl, "The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability," IEEE Journal of Solid-State Circuits, Vol. 36, No. 4, pp. 658-665, April 2001.