A high-performance, low leakage, and stable SRAM row-based back-gate biasing scheme in FinFET technology

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2007, Pages 665-670

  Joshi, Rajiv V ^a   Kim, Keunwoo ^a   Williams, Richard Q ^b   Nowak, Edward J ^b   Chuang, Ching Te ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING LANGUAGES; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUITS; POLYSILICON; STATIC RANDOM ACCESS STORAGE;

BIASING SCHEMES; LOW LEAKAGES; POLYSILICON GATES; STAND-BY LEAKAGES;

EMBEDDED SYSTEMS;

EID: 47649089640     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2007.182     Document Type: Conference Paper

References (8)

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2. Y. Liu, et al., IEEE Elec. Dev. Lett., pp.510-512, July 2004.
3. E. Nowak, et al., IEEE Cir. Dev. Mag., Jan/Feb, 2004, pp. 20-31.
4. C. H. Kim et al., ISLPED, 2003, pp. 6-9.
5. H. Ananthan et al. ISLPED, 2004, pp. 8-13.
6. MEDICI, Synopsys Inc., Mountain View, CA.
7. W. Henkels et al., US6279144, Aug 21, 2001.
8. L. Chang et al. Symp. VLSI Tech., 2005, pp. 128-129.