Statistical modeling and simulation of threshold variation under random dopant fluctuations and line-edge roughness

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 19, Issue 6, 2011, Pages 987-996

  Ye, Yun ^a   Liu, Frank ^b   Chen, Min ^a   Nassif, Sani ^b   Cao, Yu ^a  

^a Arizona State University   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

Atomistic simulation; gate slicing; line edge roughness; non rectangular gate; random dopant fluctuations; threshold voltage; variation

Indexed keywords

ATOMISTIC SIMULATIONS; GATE SLICING; LINE EDGE ROUGHNESS; NON-RECTANGULAR GATE; RANDOM DOPANT FLUCTUATION; VARIATION;

COMPUTER SIMULATION; DESIGN; FIELD EFFECT TRANSISTORS; THRESHOLD VOLTAGE;

SPICE;

EID: 84857355231     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2010.2043694     Document Type: Article

References (46)

1. "International Technology Roadmap for Semiconductors," 2006.
2. K. Bernstein, D. J. Frank, A. E. Gattiker, W. Haensch, B. L. Ji, S. R. Nassif, E. J. Nowak, D. J. Pearson, and N. J. Rohrer, "High-performance CMOS variability in the 65-nm regime and beyond," IBM J. Res. Dev., vol. 50, no. 4/5, pp. 433-449, Jul./Sep. 2006. (Pubitemid 44364163)
3. R. W. Keyes, "Physical limits in digital electronics," Proc. IEEE, vol. 63, no. 5, pp. 740-766, May 1975.
4. B. Hoeneisen and C. A. Mead, "Fundamental limitations in microelectronics-I. MOS technology," Solid-State Electron., vol. 15, no. 7, p. 819, 1972.
5. W. Zhao and Y. Cao, "New generation of predictive technology model for sub-45 nm design exploration," IEEE Trans. Electron Devices vol. 53, no. 11, pp. 2816-2823, Nov. 2006. (Pubitemid 44680679)
6. T. Mizuno, J. Okamura, and A. Toriumi, "Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFETs," IEEE Trans. Electron Devices, vol. 41, no. 11, pp. 2216-2221, Nov. 1994.
7. T. Mizuno, "Influence of statistical spatial-nonuniformity of dopant atoms on threshold voltage in a system of many MOSFET's," Japan. J. Appl. Phys., vol. 35, pp. 842-848, 1996.
8. T. Hagivaga, K. Yamaguchi, and S. Asai, "Threshold voltage variation in very smallMOStransistors due to local dopant fluctuations," in Proc. Symp. VLSI Technol., 1982, pp. 46-47. (Pubitemid 14556790)
9. K. Nishiohara, N. Shiguo, and T. Wada, "Effects of mesoscopic fluctuations in dopant distributions on MOSFET threshold voltage," IEEE Trans. Electron Devices, vol. 39, no. 3, pp. 634-639, Mar. 1992.
10. H.-S.Wong and Y. Taur, "Three-dimensional 'atomistic' simulation of discrete random dopant distribution effects in sub-0.1 μmMOSFET's," in Proc. IEDM, 1993, pp. 705-708.
11. Y. Taur, D. A. Buchanan, W. Chen, D. J. Frank, K. E. Ismail, S.-H. Lo, G. A. Sai-Halasz, R. G. Viswanathan, H.-J. C. Wann, S. J. Wind, and H.-S. Wong, "CMOS scaling into the nanometer regime," Proc. IEEE, vol. 85, no. 4, pp. 486-504, Apr. 1997.
12. V. K. De, X. Tang, and J. D. Meindl, "Random MOSFET parameter fluctuation limits to gigascale integration (GSI)," in Proc. Symp. VLSI Technol., 1996, pp. 198-199.
13. D. J. Frank, Y. Taur,M. Ieong, and H.-S. P.Wong, "Monte Carlo modeling of threshold variation due to dopant fluctuations," in Proc. Symp. VLSI Circuits, 1999, pp. 171-172. (Pubitemid 32214254)
14. K. Takeuchi, T. Tatsumi, and A. Furukawa, "Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuations," in Proc. IEDM, 1996, pp. 841-844.
15. K. Takeuchi, T. Fukai, T. Tsunomura, A. T. Putra, A. Nishida, S. Kamohara, and T. Hiramoto, "Understanding random threshold voltage fluctuation by comparing multiple Fabs and technologies," in Proc. IEDM, 2007, pp. 467-470.
16. A. Asenov, "Random dopant induced threshold voltage lowering and fluctuations in sub 0.1 micron MOSFETs: A 3D 'atomistic' simulation study," IEEE Trans. Electron Devices, vol. 45, no. 12, pp. 2505-2513, Dec. 1998. (Pubitemid 128736693)
17. A. Asenov, G. Slavcheva, A. R. Brown, J. H. Davies, and S. Saini, "Increase of the random dopant induced threshold fluctuations and lowering in sub-100 nm MOSFETs due to quantum effects: A 3-D density-gradient simulation study," IEEE Trans. Electron Devices, vol. 48, no. 4, pp. 722-729, Apr. 2001. (Pubitemid 32372233)
18. A. Asenov, A. R. Brown, J. H. Davies, S. Kaya, and G. Slavcheva, "Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs," IEEE Trans. Electron Devices, vol. 50, no. 9, pp. 1837-1852, Sep. 2003.
19. T. Yamaguchi, H. Namatsu, M. Nagase, K. Yamazaki, and K. Kurihara, "Nanometer-scale linewidth fluctuations caused by polymer aggregates in resist films," Appl. Phys. Lett., vol. 71, no. 16, pp. 2388-2390, 1997. (Pubitemid 127615783)
20. T. Yamaguchi, H. Namatsu, M. Nagase, K. Kurihara, and Y. Kawai, "Line-edge roughness characterized by polymer aggregates in photoresists," in Proc. SPIE, 1999, vol. 3678, no. 1, pp. 617-624.
21. D. L. Goldfarb, A. P. Mahorowala, G. M. Gallatin, K. E. Petrillo, K. Temple, M. Angelopoulos, S. Rasgon, H. H. Sawin, S. D. Allen, M. C. Lawson, and R. W. Kwong, "Effect of thin-film imaging on line edge roughness transfer to underlayers during etch processes," J. Vacuum Sci. Technol. B, vol. 22, no. 2, pp. 647-653, 2004.
22. H. Namatsu, M. Nagase, T. Yamaguchi, K. Yamazaki, and K. Kurihara, "Influence of edge roughness in resist patterns on etched patterns," J. Vacuum Sci. Technol. B, vol. 16, no. 6, pp. 3315-3321, Nov. 1998. (Pubitemid 128600927)
23. J. A. Croon, A. R. Brown, A. Asenov, D. Magot, and T. Linton, "Line edge roughness: Characterization, modeling and impact on device behavior," in Proc. IEDM, 2002, pp. 307-310.
24. S. Kaya, A. R. Brown, A. Asenov, D. Magot, and T. Linton, "Analysis of statistical fluctuations due to line edge roughness in sub 0.1 μm MOSFETs," in Simulation of Semiconductor Processes and Devices. New York: Springer, 2001.
25. P. Oldiges, Q. Lin, K. Pertillo, M. Sanchez, M. Ieong, and M. Hargrove, "Modeling line edge roughness effects in sub 100 nm gate length devices," in Proc. SISPAD, 2000, pp. 131-134.
26. S. Xiong and J. Bokor, "A simulation study of gate line edge roughness effects on doping profiles of short-channel mosfet devices," IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 228-232, Feb. 2004.
27. S.-D. Kim, H. Wada, and J. C. S. Woo, "TCAD-based statistical analysis and modeling of gate line-edge roughness effect on nanoscale MOS transistor performance and scaling," IEEE Trans. Semiconduct. Manuf., vol. 17, no. 2, pp. 192-200, May 2004.
28. B. Cheng, S. Roy, G. Roy, F. Adamu-Lema, and A. Asenov, "Impact of intrinsic parameter fluctuations in decanano MOSFETs on yield and functionality of SRAM cells," Elsevier Solid-State Electron., vol. 49, pp. 740-746, 2005. (Pubitemid 40340023)
29. Y. Nakagome, M. Horiguchi, T. Kawahara, and K. Itoh, "Review and future prospects of low-power RAM circuits," IBM J. Res. Dev., vol. 47, no. 5/6, pp. 525-552, Sep./Nov. 2006.
30. Y. Ye, F. Liu, S. Nassif, and Y. Cao, "Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness," in Proc. DAC, 2008, pp. 900-905.
31. S. X. Shi, P. Yu, and D. Z. Pan, "A unified non-rectangular device and circuit simulation model for timing and power," in Proc. ICCAD, 2006, pp. 423-428.
32. W. J. Poppe, L. Capodieci, J. Wu, and A. Neureuther, "From poly line to transistor: Building BSIM models for non-rectangular transistors," in Proc. SPIE, 2006, vol. 6156, pp. 235-243.
33. R. Singhal, A. Balijepalli, A. Subramaniam, F. Liu, S. Nassif, and Y. Cao, "Modeling and analysis of non-rectangular gate for post-lithography circuit simulation," in Proc. DAC, 2007, pp. 823-828. (Pubitemid 47130079)
34. P. Gupta, A. Kahng, Y. Kim, S. Shah, and D. Sylvester, "Modeling of non-uniform device geometries for post-lithography circuit analysis," in Proc. SPIE, 2006, vol. 6156, pp. 61560U1-61560U10.
35. J. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G.Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433-1440, Oct. 1989.
36. K. Takeuchi, "Channel size dependence of dopant-induced threshold voltage fluctuation," in Proc. Symp. VLSI Technol., 1998, pp. 72-73.
37. A. Subramaniam, R. Singal, and Y. Cao, "Design rule optimization of regular layout for leakage reduction in nanoscale design," in Proc. ASP-DAC, 2008, pp. 474-479.
38. J. Wu, J. Chen, and K. Liu, "Transistor width dependence of LER degradation to CMOS device characteristics," in Proc. SISPAD, 2002, pp. 95-98.
39. "Sentaurus Device User Guide," ver. A-2008.09, Sep. 2008.
40. Z. H. Liu, C. Hu, J. H. Huang, T. Y. Chan, M. C. Jeng, P. K. Ko, and Y. C. Cheng, "Threshold voltage model for deep-submicrometer MOSFETs," IEEE Trans. Electron Devices, vol. 40, no. 1, pp. 86-95, Jan. 1993. (Pubitemid 23631449)
41. T. Jhaveri et al., "Maximization of layout printability/ manufacturability by extreme layout regularity," J. Micro/Nanolitho., MEMS MOEMS, vol. 6, no. 3, p. 031011, Jul.-Sep. 2007.
42. C. Bencher, Y. Chen, H. Dai, W. Montgomery, and L. Huli, "22 nm halfpitch patterning by CVD spacer self alignment double patterning (SADP)," in Proc. SPIE, 2008, vol. 6924, pp. 69244E1-69244E7.
43. S. Sardo, F. Giacometti, S. Doneda, U. Colombo, M. Di Muri, A. Donghi, R. Morson, G. Mutinati, A. Nottola, M. Gentili, and M. C. Ubaldi, "Line edge roughness (LER) reduction strategy for SOI waveguides fabrication," Microelectron. Eng., vol. 85, no. 5-6, pp. 1210-1213, May-Jun. 2008.
44. P. P. Naulleau and G. Gallatin, "Spatial scaling metrics of mask-induced line-edge roughness," J. Vacuum Sci. Technol. B, vol. 26, no. 6, pp. 1903-1910, Nov. 2008.
45. M. Chandhok, K. Frasure, E. S. Putna, T. R. Younkin, W. Rachmady, U. Shah, and W. Yueh, "Improvement in linewidth roughness by postprocessing," J. Vacuum Sci. Technol. B, vol. 26, no. 6, pp. 2265-2270, Nov. 2008.
46. C. Alexander, G. Roy, and A. Asenov, "Random-dopant-induced drain current variation in nano-MOSFETs: A three-dimensional self-consistent Monte Carlo simulation study using "ab initio" ionized impurity scattering," IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 3251-3258, Nov. 2008.