-
1
-
-
0038294739
-
Microlithography: Trends, challenges, solutions, and their impact on design
-
A. K. Wong, "Microlithography: Trends, challenges, solutions, and their impact on design," IEEE Micro, vol. 23, pp. 12-21,2003.
-
(2003)
IEEE Micro
, vol.23
, pp. 12-21
-
-
Wong, A.K.1
-
2
-
-
27944483718
-
-
Jie Yang, Luigi Capodieci, and D. M. Sylvester, Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions, presented at DAC, 2005.
-
Jie Yang, Luigi Capodieci, and D. M. Sylvester, "Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions," presented at DAC, 2005.
-
-
-
-
3
-
-
46149095686
-
-
H. Fukutome, T. Aoyama, Y. Momiyama, T. Kubo, Y. Tagawa, and H. Arimoto, Direct evaluation of gate line edge roughness impact on extension profiles in sub-50nm N-MOSFETs, presented at IEDM, 2004.
-
H. Fukutome, T. Aoyama, Y. Momiyama, T. Kubo, Y. Tagawa, and H. Arimoto, "Direct evaluation of gate line edge roughness impact on extension profiles in sub-50nm N-MOSFETs," presented at IEDM, 2004.
-
-
-
-
4
-
-
0036927513
-
-
J. A. Croon, G. Storms, S. Winkelmeier, I. Pollentier, M. Ercken, S. Decoutere, W. Sansen, and H. E. Maes, Line edge roughness: characterization, modeling and impact on device behavior, presented at IEDM, 2002.
-
J. A. Croon, G. Storms, S. Winkelmeier, I. Pollentier, M. Ercken, S. Decoutere, W. Sansen, and H. E. Maes, "Line edge roughness: characterization, modeling and impact on device behavior," presented at IEDM, 2002.
-
-
-
-
5
-
-
0036928972
-
-
T. Linton, M. Chandhok, B. J. Rice, and G. Schrom, Determination of the line edge roughness specification for 34 nm devices, presented at IEDM, 2002.
-
T. Linton, M. Chandhok, B. J. Rice, and G. Schrom, "Determination of the line edge roughness specification for 34 nm devices," presented at IEDM, 2002.
-
-
-
-
6
-
-
0442326805
-
A simulation study of gate line edge roughness effects on doping profiles of short-channel MOSFET devices
-
S. Xiong and J. Bokor, "A simulation study of gate line edge roughness effects on doping profiles of short-channel MOSFET devices," TED, vol. 51, pp. 228, 2004.
-
(2004)
TED
, vol.51
, pp. 228
-
-
Xiong, S.1
Bokor, J.2
-
7
-
-
2642552225
-
TCAD-based statistical analysis and modeling of gate line-edge roughness effect on nanoscale MOS transistor performance and scaling
-
K. Seong-Dong, H. Wada, and J. C. S. Woo, "TCAD-based statistical analysis and modeling of gate line-edge roughness effect on nanoscale MOS transistor performance and scaling," Transactions Semiconductor Manufacturing, vol. 17, pp. 192, 2004.
-
(2004)
Transactions Semiconductor Manufacturing
, vol.17
, pp. 192
-
-
Seong-Dong, K.1
Wada, H.2
Woo, J.C.S.3
-
8
-
-
46149117436
-
-
K. Cao, J. Hu, and S. Dobre, Standard Cell Characterization Considering Lithography Induced Variations, presented at TAU, 2006.
-
K. Cao, J. Hu, and S. Dobre, "Standard Cell Characterization Considering Lithography Induced Variations," presented at TAU, 2006.
-
-
-
-
9
-
-
25144515392
-
Toward Through-Process Layout Quality Metrics
-
F.-L. Heng, J.-F. Lee, and P. Gupta, "Toward Through-Process Layout Quality Metrics," SPIE, 2005.
-
(2005)
SPIE
-
-
Heng, F.-L.1
Lee, J.-F.2
Gupta, P.3
-
10
-
-
33745608353
-
-
W. J. Poppe, L. Capodieci, J. Wu, and A. Neureuther, From Poly Line to Transistor: Building BSIM Models for Non-Rectangular Transistors, presented at SPIE, 2006.
-
W. J. Poppe, L. Capodieci, J. Wu, and A. Neureuther, "From Poly Line to Transistor: Building BSIM Models for Non-Rectangular Transistors," presented at SPIE, 2006.
-
-
-
-
11
-
-
46149098284
-
-
http://www-device.eecs.berkeley.edu/∼bsim3/.
-
"http://www-device.eecs.berkeley.edu/∼bsim3/."
-
-
-
-
12
-
-
46149111855
-
-
http://eas.asu.edu/∼ptm/.
-
"http://eas.asu.edu/∼ptm/."
-
-
-
-
15
-
-
0032592096
-
Design challenges of technology scaling
-
S. Borkar, "Design challenges of technology scaling," IEEE Micro, vol. 19, pp. 23-29, 1999.
-
(1999)
IEEE Micro
, vol.19
, pp. 23-29
-
-
Borkar, S.1
|