Transistor width dependence of LER degradation to CMOS device characteristics

International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Volumn 2002-January, Issue , 2002, Pages 95-98

  Wu, J ^a   Chen, Jihong ^a   Liu, Kaiping ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

Clouds; CMOS technology; Degradation; Frequency; Instruments; Intrusion detection; Optimization methods; Scattering; Shape; Silicon

Indexed keywords

CLOUDS; CMOS INTEGRATED CIRCUITS; DEGRADATION; INSTRUMENTS; INTRUSION DETECTION; IONS; ROUGHNESS MEASUREMENT; SCATTERING; SEMICONDUCTOR DEVICES; SILICON;

CMOS TECHNOLOGY; DEVICE CHARACTERISTICS; FREQUENCY; LINE EDGE ROUGHNESS; LOW-SPATIAL FREQUENCY; OPTIMIZATION METHOD; SHAPE; TRANSISTOR GATE LENGTH;

TRANSISTORS;

EID: 0012303666     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SISPAD.2002.1034525     Document Type: Conference Paper

References (4)

1. T. Linton, M. Giles, and P. Packan. "The impact of line edge roughness on 100nm device performance," IEEE Silicon Nanoelectronics Workshop, P. 82, 1999.
2. T. Yamaguchi et al., Microprocesses and Nanotechnology 99, P. 158
3. P. Oldiges, Q. Lin, K. Petrillo, M. Sanchez, M. Ieong, and M.Hargrove, "Modeling Line Edge Roughness Effects in sub 100 nm Gate Length Devices," SISPAD 2000, P. 131
4. Carlos H. Diaz, Hun-Jan Tao, Yao-Ching Ku, Anthony Yen and Konrad Young, "Analytical Model For Gate Line-Edge Roughness (LER) Effects on Technology Scaling", IEEE electron device letters. Vol. 22, No. 6, June 2001.