Design rule optimization of regular layout for leakage reduction in nanoscale design

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2008, Pages 474-479

  Subramaniam, Anupama R ^a   Singhal, Ritu ^a   Wang, Chi Chao ^a   Cao, Yu ^a  

^a Arizona State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

65NM TECHNOLOGY; ACTIVE POWER; AREA PENALTY; DESIGN AUTOMATION CONFERENCE; DESIGN RULES; LEAKAGE REDUCTION; NANO-SCALE DESIGN; SOUTH PACIFIC; SUB-WAVELENGTH; SYSTEMATIC PROCEDURE;

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; INDUSTRIAL ENGINEERING; LEAKAGE CURRENTS; NANOTECHNOLOGY; OPTIMIZATION; SPEED;

LAWS AND LEGISLATION;

EID: 49549107717     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2008.4483997     Document Type: Conference Paper

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