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Volumn 51, Issue 6, 2007, Pages 747-756

IBM POWER6 SRAM arrays

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; POWER SUPPLY CIRCUITS; SILICON ON INSULATOR TECHNOLOGY; STATIC RANDOM ACCESS STORAGE;

EID: 37549057592     PISSN: 00188646     EISSN: 00188646     Source Type: Journal    
DOI: 10.1147/rd.516.0747     Document Type: Article
Times cited : (18)

References (6)
  • 1
    • 0031624839 scopus 로고    scopus 로고
    • 2 Full-CMOS SRAM Cell with Aspect Ratio of 0.63 in a High-Performance 0.25 μm-Generation CMOS Technology
    • Digest of Technical Papers, June 9-11
    • 2 Full-CMOS SRAM Cell with Aspect Ratio of 0.63 in a High-Performance 0.25 μm-Generation CMOS Technology," 1998 Symposium on VLSI Technology, Digest of Technical Papers, June 9-11, 1998, pp. 68-69.
    • (1998) Symposium on VLSI Technology , vol.1998 , pp. 68-69
    • Kim, K.J.1    Youn, J.M.2    Kim, S.B.3    Kim, J.H.4    Hwang, S.H.5    Kim, K.T.6    Shin, Y.S.7


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.