A high density, low leakage, 5T SRAM for embedded caches

ESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference

Volumn , Issue , 2004, Pages 215-218

  Carlson, Ingvar ^a   Andersson, Stefan ^a   Natarajan, Sreedhar ^a   Alvandpour, Atila ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; MICROPROCESSOR CHIPS; RANDOM ACCESS STORAGE; ROBUSTNESS (CONTROL SYSTEMS); TRANSISTORS;

5T SRAM; EMBEDDED CACHES; HIGH-DENSITY STATIC EMBEDDED MEMORY UTILIZATION; HIGH-VOLUME MICROPROCESSORS;

LEAKAGE CURRENTS;

EID: 17644390667     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. H. Tran, "Demonstration of 5T SRAM and 6T Dual-Port RAM Cell Arrays," Symposium on VLSI Circuits, pp. 68-69, Jun. 1996.
2. E. Seevinck, F. J. List and J. Lohstroh, "Static-Noise Margin Analysis of MOS SRAM Cells," IEEE JSSC, VOL. SC-22, NO.5, pp.748-754, Oct. 1987.
3. J. Lohstroh, E. Seevinck and J. de Groot, "Worst-Case Static Noise Margin Criteria for Logic Circuits and Their Mathematical Equivalence," IEEE JSSC, VOL. SC-18, NO. 6, pp. 803-807, Dec. 1983.
4. A. Alvandpour, D. Somasekhar, R. Krishnamurthy, V. De, S. Borkar and C. Svensson, "Bitline leakage equalization for sub - 100nm caches," European Solid-state Circuits, 2003, ESSCIRC'03. Conference on, pp. 401-404, Sept. 2003.