Evaluation of differential vs. single-ended sensing and asymmetric cells in 90nm logic technology for on-chip caches

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 963-966

  Ye, Yibin ^a   Khellah, Muhammad ^a   Somasekhar, Dinesh ^a   De, Vivek ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; BUFFER STORAGE; ELECTRIC POWER UTILIZATION; ENERGY CONSERVATION; FORMAL LOGIC; SWITCHING;

LOGIC TECHNOLOGY; POWER SAVINGS; SENSE AMPLIFIER OFFSET; SIGNAL ARRAYS; SINGLE-ENDED SENSING;

STATIC RANDOM ACCESS STORAGE;

EID: 34547298101     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

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3. Yibin Ye, Khellah M, Somasekhar D, Farhang A, De V, "A 6 GHz, 16 Kbytes L1 cache in a 100nm dual-Vt technology using a bitline leakage reduction (BLR) technique," 2002 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 50-51, 13-15 June 2002.
4. Agawa K, Hara H, Takayanagi T, Kuroda T, "A bit-line leakage compensation scheme for low-voltage SRAM's," 2000 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 70-71, 15-17 June 2000.