Weak Write Test Mode: An SRAM cell stability design for test technique

IEEE International Test Conference (TC)

Volumn , Issue , 1997, Pages 1043-1052

  Meixner, Anne ^a   Banik, Jash ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC FAULT CURRENTS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; SEMICONDUCTING SILICON;

STATIC RANDOM ACCESS STORAGE (SRAM) CELLS; WEAK WRITE TEST MODE (WWTM);

RANDOM ACCESS STORAGE;

EID: 0031381197     PISSN: 10893539     EISSN: None     Source Type: None    
DOI: 10.1109/TEST.1997.639732     Document Type: Conference Paper

References (8)

1. A.J. van de Goor Testing Semiconductor Memories: Theory and Practice 1991 John Wiley & Sons England, West Sussex
2. R. Dekker A Realistic Fault Model and Test Algorithms for Static Random Access Memories IEEE Trans on Computer C-9 6 567 572 1990
3. R. Rajsuman An Algorithm and Design to test Random Access Memories IEEE International Symposium on Circuits and Systems 439 442 IEEE International Symposium on Circuits and Systems 1992
4. M. Sachdev Reducing the CMOS RAM Test Complexity with Iddq and Voltage Testing Journal of Electronic Testing: Theory and Applications 5 191 202 1995
5. C. Kuo Soft-Defect Detection (SDD) Technique for a High-Reliability CMOS SRAM IEEE Journal of Solid-State Circuits 25 1 61 67 February 1990
6. M. Bohr A High Performance 0.3 μm Logic Technology for 3.3V and 2.5V Operation IDEM 10.2.1 10.2.4 Dec 1994