2 GHz cycle, 430 ps access time 34 Kb L1 directory SRAM in 1.5 V, 0.18 μm CMOS bulk technology

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2000, Pages 222-225

  Joshi, R V ^a   Kowalczyk, S P ^a   Chan, Y H ^a   Huott, W V ^a   Wilson, S C ^a   Scharff, G J ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; CMOS INTEGRATED CIRCUITS; INTERFACES (COMPUTER); RANDOM ACCESS STORAGE; RESPONSE TIME (COMPUTER SYSTEMS);

ARRAY-BUILT-IN-SELF-TEST; PSEUDO-STATIC CIRCUITS;

VLSI CIRCUITS;

EID: 0033683110     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)