Read and write circuit assist techniques for improving vccmin of dense 6T SRAM cell

Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT

Volumn , Issue , 2008, Pages 185-188

  Khellah, Muhammad M ^a   Keshavarzi, Ali ^a   Somasekhar, Dinesh ^a   Karnik, Tanay ^a   De, Vivek ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS INDUSTRY; INTEGRATED CIRCUITS; STATIC RANDOM ACCESS STORAGE; TECHNOLOGY;

6T-SRAM; CIRCUIT TECHNIQUES; INTEGRATED CIRCUIT DESIGN; INTERNATIONAL CONFERENCES;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 51849165535     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICICDT.2008.4567275     Document Type: Conference Paper

References (10)

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4. H Pilo et al, "An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage," JSSC, vol. 42, no. 4, April 2007.
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9. M. Clinton, "Variability and SRAM Implications," 2007 DAC Tutorial
10. H. Yamauchi, "Embedded SRAM Design and Scaling Trend," part of the 2008 ISSCC Forum on Embedded Memory Design.