Performance and yield benefits of quasi-planar bulk CMOS technology for 6-T SRAM at the 22-nm node

IEEE Transactions on Electron Devices

Volumn 58, Issue 7, 2011, Pages 1846-1854

  Shin, Changhwan ^a   Damrongplasit, Nattapol ^a   Sun, Xin ^a   Tsukamoto, Yasumasa ^a,b   Nikolic, Borivoje ^a   Liu, Tsu Jae King ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

Complementary metaloxidesemiconductor (CMOS); metaloxidesemiconductor field effect transistor (MOSFET); static random access memory (SRAM); variability

Indexed keywords

3D SIMULATIONS; 6-SIGMA; BULK CMOS; CELL STRUCTURE; CELL YIELDS; COMPLEMENTARY METALOXIDESEMICONDUCTOR (CMOS); DOPING PROFILES; GATE LENGTH; LINE EDGE ROUGHNESS; MOSFETS; OPERATING VOLTAGE; SRAM CELL; STANDBY POWER; STATIC RANDOM ACCESS MEMORY; THREE-DIMENSIONAL (3-D) DEVICE; THRESHOLD VOLTAGE VARIABILITY; VARIABILITY;

CELLS; CMOS INTEGRATED CIRCUITS; ELECTRON BEAM LITHOGRAPHY; MOSFET DEVICES; THREE DIMENSIONAL; THREE DIMENSIONAL COMPUTER GRAPHICS;

STATIC RANDOM ACCESS STORAGE;

EID: 79959500502     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2011.2139213     Document Type: Article

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