SRAM design in fully-depleted SOI technology

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Volumn , Issue , 2010, Pages 1707-1710

  Nikolić, Borivoje ^a   Shin, Changhwan ^a   Cho, Min Hee ^a   Sun, Xin ^a   Liu, Tsu Jae King ^a   Nguyen, Bich Yen ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b SOITEC USA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3D DEVICE SIMULATION; ANALYTICAL MODELING; BULK CMOS; BURIED OXIDES; FULLY DEPLETED; SOI FINFETS; SOI TECHNOLOGY; SOI-MOSFETS; SRAM CELL; SRAM DESIGN;

FABRICS; LOGIC DESIGN; SILICON ON INSULATOR TECHNOLOGY; THREE DIMENSIONAL;

STATIC RANDOM ACCESS STORAGE;

EID: 77955997314     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2010.5537520     Document Type: Conference Paper

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