A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2008, Pages 212-213

  Nii, K ^a   Yabuuchi, M ^a   Tsukamoto, Y ^a   Ohbayashi, S ^a   Oda, Y ^b   Usui, K ^c   Kawamura, T ^a   Tsuboi, N ^a   Iwasaki, T ^a   Hashimoto, K ^a   Makino, H ^a   Shinohara, H ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b Shikino High Tech Corporation   (Japan)

^c Daioh Electric Corporation   (Japan)

Author keywords

45nm; 6T; 8T; CMOS; DVFS; SRAM; Stability

Indexed keywords

CMOS INTEGRATED CIRCUITS; CONVERGENCE OF NUMERICAL METHODS; DYNAMIC RANDOM ACCESS STORAGE; STATIC RANDOM ACCESS STORAGE; TIMING CIRCUITS; VLSI CIRCUITS; VOLTAGE SCALING;

45NM; DESIGN SOLUTIONS; DVFS; DYNAMIC VOLTAGE AND FREQUENCY SCALING; PASSIVE RESISTANCE; PROCESS VARIATION; ROBUST OPERATION; SUPPRESSION TECHNIQUE;

DYNAMIC FREQUENCY SCALING;

EID: 51949090717     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2008.4586011     Document Type: Conference Paper

References (3)

1. S. Ohbayashi et al., IEEE JSSC, Vol.42, No.4, pp820-829, 2007.
2. M. Yabuuchi et al., ISSCC Digest, pp508-509, 2007.
3. Shibata et al., IEEE JSSC, Vol.41, No.3, pp728-742, 2006.