Segmented tri-gate bulk CMOS technology for device variability improvement

Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010

Volumn , Issue , 2010, Pages 114-115

  Tsai, C H ^a   King Liu, T J ^b   Tsai, S H ^a   Chang, C F ^a   Tseng, Y M ^a   Liao, R ^a   Huang, R M ^a   Liu, P W ^a   Tsai, C T ^a   Shin, C ^b   Nikolic B ^b   Liang, C W ^a  

^a UNITED MICROELECTRONICS CORPORATION   (Taiwan)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BODY DOPING; BULK CMOS; BULK MOSFET; CMOS TECHNOLOGY; DEVICE PERFORMANCE; ELECTROSTATIC INTEGRITY; FIN WIDTHS; MOSFETS; OPERATING VOLTAGE; PLANAR CELLS; SRAM CELL; STATIC NOISE MARGIN; TRANSISTOR PERFORMANCE; TRI-GATE STRUCTURES; TRIGATE; WRITE MARGIN;

CMOS INTEGRATED CIRCUITS; SEMICONDUCTING SILICON; STATIC RANDOM ACCESS STORAGE; TECHNOLOGY;

MOSFET DEVICES;

EID: 77957905146     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2010.5488926     Document Type: Conference Paper

References (8)

1. E. Josse et al., IEDM Tech. Dig. 293 (2006)
2. K. Nii et al., Symp. VLSI Circuits Dig. 212 (2008)
3. A. Asenov et al., IEEE TED 46 1718 (1999)
4. K. Takeuchi et al., IEEE TED 48 1995 (2001)
5. K. J. Kuhn, IEDM Tech. Dig. 471 (2007)
6. C.-H. Lee et al., Symp. VLSI Tech. Dig. 130 (2004)
7. X. Sun and T.-J. King Liu, IEEE TED 56 2840 (2009)
8. X. Sun et al., IEEE EDL 29 491 (2008)