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Volumn , Issue , 2010, Pages 142-145

Tri-Gate bulk CMOS technology for improved SRAM scalability

Author keywords

[No Author keywords available]

Indexed keywords

6T-SRAM; AREA SCALING; BULK CMOS; BULK MOSFET; CMOS TECHNOLOGY; HIGH YIELD; SIMPLE APPROACH; TRIGATE; VOLTAGE-SCALING; WRITE MARGIN;

EID: 78649956124     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2010.5618437     Document Type: Conference Paper
Times cited : (7)

References (14)
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  • 3
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    • Tri-gate bulk MOSFET design for CMOS scaling to the end of the roadmap
    • X. Sun et al., "Tri-gate bulk MOSFET design for CMOS scaling to the end of the roadmap, " IEEE Electron Device Letters, Vol. 29, No. 5, pp. 491-493, 2008.
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    • Sun, X.1
  • 4
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  • 5
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  • 7
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  • 9
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  • 10
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  • 12
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.