Performance and area scaling benefits of FD-SOI technology for 6-T SRAM cells at the 22-nm node

IEEE Transactions on Electron Devices

Volumn 57, Issue 6, 2010, Pages 1301-1309

  Shin, Changhwan ^a   Cho, Min Hee ^a   Tsukamoto, Yasumasa ^a,b   Nguyen, Bich Yen ^c   Mazuré, Carlos ^c   Nikolić, Borivoje ^a   Liu, Tsu Jae King ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b RENESAS TECHNOLOGY CORP   (Japan)

^c SOITEC USA   (United States)

Author keywords

CMOS; MOSFET; Silicon on insulator (SOI); SRAM; Variability

Indexed keywords

3D DEVICE SIMULATION; AREA SCALING; CMOS TECHNOLOGY; DOPING PROFILES; FULLY DEPLETED SILICON-ON-INSULATOR; MOS-FET; MOSFETS; OPERATING VOLTAGE; READ CURRENT; SILICON-ON-INSULATORS; SIX-SIGMA; SOI TECHNOLOGY; SRAM CELL; THRESHOLD VOLTAGE VARIABILITY; WRITE MARGIN;

CMOS INTEGRATED CIRCUITS; FINITE DIFFERENCE METHOD; MOSFET DEVICES; SILICON ON INSULATOR TECHNOLOGY;

SEMICONDUCTING SILICON COMPOUNDS;

EID: 77952746075     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2010.2046070     Document Type: Article

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