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Volumn , Issue , 2008, Pages

Scaling of 32nm low power SRAM with high-K metal gate

Author keywords

[No Author keywords available]

Indexed keywords

BULK TECHNOLOGIES; CELL PROCESS; CONTACT PROCESS; LOW POWER APPLICATIONS; LOW-POWER; LOW-POWER SRAM; METAL GATES; READ CURRENTS; VT MISMATCHES; WRITE MARGINS;

EID: 64549129929     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796660     Document Type: Conference Paper
Times cited : (34)

References (3)
  • 1
    • 33947694725 scopus 로고    scopus 로고
    • H. Pilo et al., IEEE J. Solid-State Circuits, 42, No.4, 4/07, p.813
    • H. Pilo et al., IEEE J. Solid-State Circuits, vol.42, No.4, 4/07, p.813


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.