The scan-DFT features of AMD's next-generation microprocessor core

Proceedings - International Test Conference

Volumn , Issue , 2010, Pages

  Yilmaz, Mahmut ^a   Wang, Baosheng ^a   Rajaraman, Jayalakshmi ^a   Olsen, Tom ^a   Sobti, Kanwaldeep ^a   Elvey, Dwight ^a   Fitzgerald, Jeff ^a   Giles, Grady ^a   Chen, Wei Yu ^a  

^a ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUDGET CONTROL; INTEGRATED CIRCUIT DESIGN;

ADVANCED MICRO DEVICES; HIGH-PERFORMANCE MICROPROCESSORS; MICROPROCESSOR CORE; NANOMETER TECHNOLOGY; POWER-SUPPLY NOISE; PROCESS VARIATION; SCAN ARCHITECTURE; VERIFICATION STRATEGY;

DESIGN FOR TESTABILITY;

EID: 79951623528     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2010.5699203     Document Type: Conference Paper

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