Selecting high-quality delay tests for manufacturing test and debug

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2006, Pages 59-67

  Lee, Hangkyu ^a   Natarajan, Suriyaprakash ^b   Patil, Srinivas ^b   Pomeranz, Irith ^a  

^a PURDUE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATIONAL BENCHMARK CIRCUITS; DEBUGGING TIMING FAILURES; FUNCTIONAL VECTORS; HIGH-QUALITY DELAY TESTS;

CIRCUIT SIMULATION; COMPUTATIONAL METHODS; COMPUTER DEBUGGING; DELAY CIRCUITS; FAILURE ANALYSIS; METRIC SYSTEM;

VLSI CIRCUITS;

EID: 38749146306     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFT.2006.57     Document Type: Conference Paper

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