Test-pattern selection for screening small-delay defects in very-deep submicrometer integrated circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 29, Issue 5, 2010, Pages 760-773

  Yilmaz, Mahmut ^a   Chakrabarty, Krishnendu ^b   Tehranipoor, Mohammad ^c  

^a ADVANCED MICRO DEVICES   (United States)

^b Duke University   (United States)

^c UNIVERSITY OF CONNECTICUT   (United States)

Author keywords

Delay test; Output deviations; Process variations; Small delay defects; Test pattern grading

Indexed keywords

DELAY DEFECTS; DELAY TESTS; OUTPUT DEVIATION; PROCESS VARIATION; SMALL-DELAY DEFECTS;

COMPUTATIONAL COMPLEXITY; DELAY CIRCUITS; ELECTRON DEVICE TESTING; INTEGRATED CIRCUITS; TESTING; TIME DELAY; TIME MEASUREMENT; TIMING CIRCUITS;

AUTOMATIC TEST PATTERN GENERATION;

EID: 77951681763     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2010.2043591     Document Type: Article

References (32)

1. N. Ahmed, M. Tehranipoor, and V. Jayaram, "Timing-based delay test for screening small delay defects, " in Proc. IEEE Design Autom. Conf., 2006, pp. 320-325. (Pubitemid 47113915)
2. X. Lin, K.-H. Tsai, C. Wang, M. Kassab, J. Rajski, T. Kobayashi, R. Klingenberg, Y. Sato, S. Hamada, and T. Aikyo, "Timing-aware ATPG for high quality at-speed testing of small delay defects, " in Proc. IEEE Asian Test Symp., 2006, pp. 139-146. (Pubitemid 46499320)
3. J. A. Waicukauski, E. Lindbloom, B. Rosen, and V. Iyengar, "Transition fault simulation, " IEEE Design Test Comput., vol. 4, no. 2, pp. 32-38, Mar. 1987.
4. R. Putman and R. Gawde, "Enhanced timing-based transition delay testing for small delay defects, " in Proc. IEEE Very Large Scale Integr. Test Symp., 2006, pp. 336-342. (Pubitemid 44761113)
5. 1Cadence, Inc. "Encounter test: Test generation and simulation reference, " product Version 3.0, 2005.
6. Mentor Graphics. "Understanding how to run timing-aware ATPG, " Application Note, 2006.
7. R. Kapur, J. Zejda, and T. W. Williams, "Fundamentals of timing information for test: How simple can we get?" in Proc. IEEE Int. Test Conf., Oct. 2007, pp. 1-7. (Pubitemid 351303679)
8. IWLS 2005 Benchmarks [Online]. Available: http://iwls.org/iwls2005/ benchmarks.html
9. M. Yilmaz, K. Chakrabarty, and M. Tehranipoor, "Test-pattern selection for screening small-delay defects in very-deep submicrometer integrated circuits, " Duke University, Tech. Rep. ECE-2009-02 [Online]. Available: http://hdl.handle.net/10161/1376
10. B. Keller, M. Tegethoff, T. Bartenstein, and V. Chickermane, "An economic analysis and ROI model for nanometer test, " in Proc. IEEE Int. Test Conf., 2004, pp. 518-524. (Pubitemid 40610051)
11. F.-F. Ferhani and E. J. McCluskey, "Classifying bad chips and ordering test sets, " in Proc. IEEE Int. Test Conf., Oct. 2006, pp. 1-10.
12. Semiconductor Industry Association. (2007) International technology roadmap for semiconductors (ITRS) [Online]. Available: http://www.itrs.net/ links/2007itrs/home2007.htm
13. Z. Wang and K. Chakrabarty, "Test-quality/cost optimization using outputdeviation-based reordering of test patterns, " IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 27, no. 2, pp. 352-365, Feb. 2008. (Pubitemid 351169648)
14. Z. Wang and K. Chakrabarty, "An efficient test pattern selection method for improving defect coverage with reduced test data volume and test application time, " in Proc. IEEE Asian Test Symp., 2006, pp. 333-338. (Pubitemid 46499348)
15. H. Lee, S. Natarajan, S. Patil, and I. Pomeranz, "Selecting high-quality delay tests for manufacturing test and debug, " in Proc. IEEE Int. Symp. Defect Fault Tolerance Very Large Scale Integr. Syst., 2006, pp. 59-70. (Pubitemid 351175374)
16. E. S. Park, M. R. Mercer, and T. W. Williams, "Statistical delay fault coverage and defect level for delay faults, " in Proc. IEEE Int. Test Conf., 1988, pp. 492-499.
17. P. Gupta and M. S. Hsiao, "ALAPTF: A new transition fault model and the ATPG algorithm, " in Proc. IEEE Int. Test Conf., 2004, pp. 1053-1060. (Pubitemid 40610111)
18. W. Qiu, J. Wang, D. M. H. Walker, D. Reddy, X. Lu, Z. Li, W. Shi, and H. Balachandran, "K longest paths per gate (KLPG) test generation for scan-based sequential circuits, " in Proc. IEEE Int. Test Conf., 2004, pp. 223-231. (Pubitemid 40610020)
19. S. Gurumurthy, R. Vemu, J. A. Abraham, and D. G. Saab, "Automatic generation of instructions to robustly test delay defects in processors, " in Proc. IEEE Eur. Test Symp., 2007, pp. 173-178. (Pubitemid 47431736)
20. H. Yan and A. D. Singh, "A new delay test based on delay defect detection within slack intervals (DDSI), " IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 11, pp. 1216-1226, Nov. 2006. (Pubitemid 44924944)
21. I. Pomeranz and S. M. Reddy, "Transition path delay faults: A new path delay fault model for small and large delay defects, " IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 1, pp. 98-107, Jan. 2008. (Pubitemid 350281191)
22. S. Bose, H. Grimes, and V. D. Agrawal, "Delay fault simulation with bounded gate delay mode, " in Proc. IEEE Int. Test Conf., Oct. 2007, pp. 1-10. (Pubitemid 351303705)
23. V. Iyengar, J. Xiong, S. Venkatesan, V. Zolotov, D. Lackey, P. Habitz, and C. Visweswariah, "Variation-aware performance verification using at-speed structural test and statistical timing, " in Proc. IEEE Int. Conf. Comput.-Aided Design, 2007, pp. 405-412.
24. V. Zolotov, J. Xiong, H. Fatemi, and C. Visweswariah, "Statistical path selection for at-speed test, " in Proc. IEEE Int. Conf. Comput.-Aided Design, 2008, pp. 624-631.
25. C. Forzan and D. Pandini, "Why we need statistical static timing analysis, " in Proc. IEEE Int. Conf. Comput. Design, 2007, pp. 91-96.
26. I. Nitta, S. Toshiyuki, and H. Katsumi, "Statistical static timing analysis technology, " Fujitsu Sci. Tech. J., vol. 43, no. 4, pp. 516-523, Oct. 2007. (Pubitemid 350084369)
27. C.-T. M. Chao, L.-C. Wang, and K.-T. Cheng, "Pattern selection for testing of deep submicron timing defects, " in Proc. IEEE Design Autom. Test Eur., vol. 2. 2004, pp. 1060-1065.
28. B. Lee, H. Li, L.-C. Wang, and M. Abadir, "Pattern selection for testing of deep submicron timing defects, " in Proc. IEEE Int. Test Conf., vol. 2. 2005, pp. 1060-1065.
29. Y. Sato, S. Hamada, T. Maeda, A. Takatori, Y. Nozuyama, and S. Kajihara, "Invisible delay quality: SDQM model lights up what could not be seen, " in Proc. IEEE Int. Test Conf., 2005, 9 p. 1210. (Pubitemid 46287619)
30. M. Yilmaz, K. Chakrabarty, and M. Tehranipoor, "Interconnect-aware and layout-oriented test-pattern selection for small-delay defects, " in Proc. IEEE Int. Test Conf., 2008, pp. 1-10.
31. M. Yilmaz, "Automated test grading and pattern selection for small-delay defects, " Ph. D. dissertation, Dept. Electr. Comput. Eng., Duke Univ., Durham, NC, Apr. 2009.
32. R. R. Wilcox, Fundamentals of Modern Statistical Methods: Substantially Improving Power and Accuracy, 2nd ed. New York: Springer, 2010, pp. 179-180.