Robust test generation for precise crosstalk-induced path delay faults

Proceedings of the IEEE VLSI Test Symposium

Volumn 2006, Issue , 2006, Pages 300-305

  Li, Huawei ^a   Shen, Peifu ^b   Li, Xiaowei ^a  

^a INSTITUTE OF COMPUTING TECHNOLOGY   (China)

^b BEIJING NORMAL UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; ELECTRIC FAULT LOCATION; MATHEMATICAL MODELS;

DELAY FAULTS; S-PCPDF MODEL; SENSITIZATION;

ROBUSTNESS (CONTROL SYSTEMS);

EID: 33751112304     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2006.60     Document Type: Conference Paper

References (18)

1. K.-T. Cheng, S. Dey, M. Rodgers, and K. Roy, "Test Challenges for Deep Sub-Micron Technologies", Proceedings of 37th Design Automation Conference, pp. 142-149, June 2000.
2. A. Rubio, N. Itazaki, X. Xu and K. Kinoshita, "An Approach to the Analysis and Detection of Crosstalk Faults in Digital VLSI Circuits", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol.13, No.3, March 1994, pp; 387-394.
3. F. Moll and A. Rubio, "Spurious Signals in Digital CMOS VLSI Circuits: A Propagation Analysis", IEEE Trans. on Circuits and Systems - II: Analog and Digital Signal Processing, Vol. 39, No. 10, October 1992, pp. 749-752.
4. R. Anglada and A. Rubio, "Logic Fault Model for Crosstalk Interferences in Digital Circuits", International Journal of Electronics, Vol. 67, No. 3, September 1989, pp. 423-425.
5. N. Itazaki, Y. Matsumoto, and K. Kinoshita, "An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits", Proceedings of Sixth Asian Test Symposium, pp. 22-27, November 1997.
6. K. T. Lee, C. Nordquist, J. A. Abraham, "Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits", Proceedings of 16th IEEE VLSI Test Symposium, pp. 34-39, April 1998.
7. W.-Y. Chen, S. K. Gupta, and M. A. Breuer, "Test Generation in VLSI Circuits for Crosstalk Noise", Proceedings of IEEE International Test Conference, pp. 641-650, October 1998.
8. W.-Y. Chen, S. K. Gupta, and M. A. Breuer, "Test Generation for Crosstalk-Induced Faults: Framework and Computational Results", Proceedings of Ninth Asian Test Symposium, pp. 305-310, December 2000.
9. W.-Y. Chen, S. K. Gupta, and M. A. Breuer, "Test Generation for Crosstalk-Induced Delay in Integrated Circuits", Proceedings of IEEE International Test Conference, pp. 191-200, October 1999.
10. K. J. Keller, H. Takahashi, K. K. Saluja, Y. Takamatsu, "On Reducing the Target Fault List of Crosstalk-Induced Delay Faults in Synchronous Sequential Circuits", Proceedings of IEEE International Test Conference, pp. 568-577, November 2001.
11. A. Krstic, J.-J. Liou, Y.-M. Jiang and K.-T. Cheng, "Delay Testing Considering Crosstalk-Induced Effects", Proceedings of IEEE International Test Conference, pp. 558-567, November 2001.
12. H. Li, Y. Zhang and X. Li, "Delay Test Pattern Generation Considering Crosstalk-Induced Effects", Proceedings of 12th Asian Test Symposium, pp. 178-183, November 2003.
13. R. Kundu and R. D. Blanton, "Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk", Proceedings of IEEE International Test Conference, pp. 122-130, October 2003.
14. H. Li and X. Li, "Selection of Crosstalk-induced Faults in Enhanced Delay Test", Journal of Electronic Testing: Theory and Applications, Vol. 21, No. 2, April 2005, pp. 181-195.
15. K.-T. Cheng and H.-C. Chen, "Classification and Identification of Nonrobust Untenable Path Delay Faults", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 8, August 1996. pp. 845-853.
16. I. Pomeranz, L. N. Reddy, and S. M. Reddy, "SPADES: A Simulator for Path Delay Faults in Sequential Circuits", Proceeding of European Conf. on Design Automation, pp. 428-432, Sept., 1992.
17. W. Long, Z. Li, S. Yang, and Y. Min, "Memory Efficient ATPG for Path Delay Faults," Proceedings of Sixth Asain Test Symposium, pp. 326-331, November 1997.
18. K. Fuchs, F. Fink, and M. H. Schulz, "DYNAMITE: An Efficient Automatic Test Pattern Generation System for Path Delay Faults", IEEE Trans. on CAD, Vol.10, No.10, Oct. 1991, pp. 1323-1335.