A gated clock scheme for low power scan testing of logic ICs or embedded cores

Proceedings of the Asian Test Symposium

Volumn , Issue , 2001, Pages 253-258

  Bonhomme, Y ^a   Girard, P ^a   Guiller, L ^a,b   Landrault, C ^a   Pravossoudovitch, S ^a  

^a LIRMM   (France)

^b SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DESIGN FOR TESTABILITY; LOGIC GATES; TIMING CIRCUITS;

EMBEDDED CORES; GATED CLOCK SCHEME; LOW POWER SCAN TESTING; SCAN PATH; TEST POWER;

INTEGRATED CIRCUIT TESTING;

EID: 0035699333     PISSN: 10817735     EISSN: None     Source Type: Journal    
DOI: 10.1109/ATS.2001.990291     Document Type: Article

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