Interconnect-aware and layout-oriented test-pattern selection for small-delay defects

Proceedings - International Test Conference

Volumn , Issue , 2008, Pages

  Yilmaz, Mahmut ^a   Chakrabarty, Krishnendu ^a   Tehranipoor, Mohammad ^b  

^a Duke University   (United States)

^b UNIVERSITY OF CONNECTICUT   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ATPG TOOLS; CHIP LAYOUT; CPU TIME; DELAY DEFECTS; DELAY FAULTS; DELAY VARIATION; HIGH-PERFORMANCE INTEGRATED CIRCUITS; INTERCONNECT DEFECTS; INTERCONNECT DELAY; LONG-PATH; OUTPUT DEVIATION; PATTERN SELECTION; POWER-SUPPLY NOISE; PROCESS VARIATION; RESISTIVE SHORTS; SELECTION METHODS; SIGNIFICANT IMPACTS;

DEFECTS; INTEGRATED CIRCUITS; METAL DETECTORS; TIME DELAY; TIME MEASUREMENT; TIMING CIRCUITS;

DELAY CIRCUITS;

EID: 67249087944     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2008.4700627     Document Type: Conference Paper

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