Simplified method for testing the IBM pipeline partial-scan microprocessor

Proceedings of the Asian Test Symposium

Volumn , Issue , 1999, Pages 321-326

  Chen, Xinghao ^a   Snethen, Tom ^a   Swenton, Joe ^a   Walther, Ron ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PIPELINED PARTIAL SCAN MICROPROCESSORS;

INTEGRATED CIRCUIT TESTING; OPTIMIZATION; PIPELINE PROCESSING SYSTEMS;

MICROPROCESSOR CHIPS;

EID: 0033330398     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (36)

1. V. D. Agrawal Cheng, D. D. Johnson, and T. Lin. A Complete Solution to the Partial Scan Problem. In Proceedings of the International Test Conference, pages 44-51, September 1987.
2. V. D. Agrawal, K.-T. Cheng, D. D. Johnson, and T. Lin. Designing Circuits with Partial Scan. IEEE Design & Test of Computers, 5(2):8-15, April 1988.
3. D. Amason, A. L. Crouch, R. Eisele, G. Giles, and M. Mateja. A Case Study of the Test Development for the 2nd Generation ColdFire Microprocessors. In Proceedings of the International Test Conference, pages 424-432, November 1997.
4. A. Carbine and D. Feltham. PENTIUM PRO Processor Design for Test and Debug. In Proceedings of the International Test Conference, pages 294-303, November 1997.
5. S. T. Chakradhar, A. Balakrishnan, and V. D. Agrawal. An Exact Algorithm for Selecting Partial Scan Flip-Flops. Journal of Electronic Testing: Theory and Applications, 7(l/2):84-93, August/October 1995.
6. K.-T. Cheng and V. D. Agrawal. An Economical Scan Design for Sequential Logic Test Generation. In Digest of Papers of the 19th Fault-Tolerant Computing Symposium, pages 28-35, June 1989.
7. K.-T. Cheng and V. D. Agrawal. A Partial Scan Method for Sequential Circuits with Feedback. IEEE Transactions on Computers, 39(4):544-548, April 1990.
8. V. Chickermane and J. H. Patel. An Optimization Based Approach to the Partial Scan Design Problem. In Proceedings of the International Test Conference, pages 377-386, November 1990.
9. V. Chickermane and J. H. Patel. A Fault Oriented Partial Scan Design Approach. In Proceedings of the International Test Conference, pages 400-403, November 1991.
10. S. Dey and S. T. Chakradhar. Design of Testable quential Circuits by Repositioning Flip-Flops. Journal of Electronic Testing: Theory and Applications, 7(1/2):105-114, August/October 1995.
11. E. B. Eichelberger and T. W. Williams. A Logic Design Structure for LSI Testability. In Proceedings of the 14th Design Automation Conference, pages 462-468, June 1977.
12. E. B. Eichelberger and T. W. Williams. A Logic Design Structure for LSI Testability. IEEE Journal of Design Automation and Fault Tolerant Computing, 2 (5): 165 178, May 1978.
13. R. S. Fetherston, I. Fliaik, and S. C. Ma. Testability Features of AMD-K6 Microprocessor. In Proceedings of the International Test Conference, pages 406-413, November 1997.
14. T. G. Foote, D. E. Hof&nan, W. V. Huott, T. J. Ko-provski, B. J. Robbins, and M. P. Kusko. Testing the 400MHz IBM Generation-4 CMOS Chip. In Piocad-ings of the International Test Conference, pages 106-114, November 1997.
15. P. Goel. An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits. IEEE Transactions on Computers, 30(3):215-222, March 1981.
16. R. Gupta and M. Breuer. Partial Scan Design of Register-Transfer Level Circuits. Journal of Electronic Testing: Theory and Applications, 7(1/2):25-46, August/October 1995.
17. R. Gupta, R. Gupta, and M. A. Breuer. BALLAST: A Methodology for Partial Scan Design. In Digest of Papers of the 19th Fault-Tolerant Computing Symposium, pages 118-125, June 1989.
18. Y. Higami, S. Kajihara, and K. Kinoshita Partial Scan Design and Test Sequence Generation Based on Reduced Scan Shift Method. Journal of Electronic Testing: Theory and Applications, 7(1/2):115-124, August/October 1995.
19. C. Hunter, E. Kofi Vida-Torku, and Johnny LeBlanc. Balancing Structured and Ad-hoc Design for Test: Testing of the Power PC™ Microprocessor. In Proceeding of the International Test Conference, pages 76-83, October 1994.
20. W. V. Huott, T. J. Koprowski, B. J. Robbins, M. P. Kusko, S. V. Pateras, D. E. Hoffman, T. G. McNamara, and T. J. Snethen. Advanced Microprocessor Test Strategy and Methodology. IBM Journal of Research and Development, 41(4/5):611-627, July/September 1997.
21. K. J. Jeong, S. Krishnaswami, B. G. Oomman, and S. Hemmady. Designers Tackle the Testability of a System-Level IC. Integrated System Design, 10(104):38-16, February 1998.
22. R. Kapur, S. Patil, T. J. Snethen, and T. W. Williams. Design of an Efficient Weighted Random Pattern Generation System. In Proceedings of the International Test Conference, pages 491-500, October 1994.
23. K. Kim and C. R. Kime. Partial Scan Flip-Flop Selection by Use of Empirical Testability. Journal of Electronic Testing: Theory and Applications, 7(1/2):47-59, August/October 1995.
24. D. H. Lee and S. M. Reddy On Determining Scan Flip-Flops in Partial-Scan. In Proceedings of the International Test Conference, pages 322-325, November 1990.
25. C.-J. Lin, Y. Zorian, and S. Bhawmik. Integration of Partial Scan and Built-in Self-Test. Journal of Electronic Testing: Theory and Applications, 7(1/2):126-137, August/October 1995.
26. H. K. T. Ma, S. Devadas, A. R. Newton, and A Sangiovanni-Vincentelli. An Incomplete Scan Design Approach to Test Generation for Sequential Machines. In Proceeding of the International Test Conference, pages 730-734, September 1988.
27. E. J. McCluskey A Survey of Design for Testability Scan Techniques. IEEE VLSI System Design, (12):38-61, December 1984.
28. H. B. Min and W. A. Rogers. A Test Methodology for Finite State Machines Using Partial Scan Design. Journal of Electronic Testing: Theory and Applications, 3(1):127-137, May 1992.
29. T. Orenstein, Z. Kohavi, and I. Pomeranz. An Optional Algorithm for Cycle Breaking in Directed Graphs. Journal of Electronic Testing: Theory and Applications, 7(1/2):71-81, August/October 1995.
30. P. S. Parikh and M. Abramovici. Testability-Based Partial Scan Analysis. Journal of Electronic Testing: Theory and Applications, 7(l/2):61-70, August/October 1995.
31. C. Pyron, Prado, and J. Golab. Next Generation PowerPC Microprocessor Test Strategy Improvements. In Proceedings of the International Test Conference, pages 414-423, November 1997.
32. J. Steensma, F. Catthoor, and H. D. Man. Partial Scan and Symbolic Test at the Register-Transfer Level. Journal of Electronic Testing: Theory and Applications, 7(l/2):7-23, August/October 1995.
33. S.-E. Tai and D. Bhattacharya. A Three-Stage Partial Scan Design Method to Ease ATPG. Journal of Electronic Testing: Theory and Applications, 7(l/2):95-104, August/October 1995.
34. E. Trischler. Design for Testability Using Incomplete Scan Path and Testability Analysis. Siemens Forsch.-u. Entwickl.-Ber, 13(2):56-61, February 1984.
35. J. A. Waicukauski. Partial Scan Using Sequential Transparency. In Proceedings of the Asia Electronic Design Automation and Test Conference, pages 201-213, August 1995.
36. J. A. Waicukauski and E. Lindbloom. Fault Detection Effectiveness of Weighted Random Patterns. In Proceedings of the International Test Conference, pages 245-255, September 1988.