-
1
-
-
3142720622
-
Delay Defect Screening Using Process Monitor Structures
-
S. Mitra, E. Volkerink, E.J. McCluskey, and S. Eichenberger, "Delay Defect Screening Using Process Monitor Structures," Proc. VTS 2004, pp. 43-48.
-
(2004)
Proc. VTS
, pp. 43-48
-
-
Mitra, S.1
Volkerink, E.2
McCluskey, E.J.3
Eichenberger, S.4
-
2
-
-
0023330236
-
Transition Fault Simulation
-
Apr
-
J.A. Waicukauski, E. Lindbloom, B.K. Rosen, and V.S. Iyengar, "Transition Fault Simulation," IEEE Design & Test of Computer, pp.32-38, Apr. 1987.
-
(1987)
IEEE Design & Test of Computer
, pp. 32-38
-
-
Waicukauski, J.A.1
Lindbloom, E.2
Rosen, B.K.3
Iyengar, V.S.4
-
3
-
-
0022307908
-
Model for Delay Faults Based Upon Paths
-
G.L. Smith, "Model for Delay Faults Based Upon Paths," Proc. ITC 1985, pp.342-349.
-
(1985)
Proc. ITC
, pp. 342-349
-
-
Smith, G.L.1
-
4
-
-
84954437245
-
Experience in Critical Path Selection for Deep Submicron Delay Test and Timing Validation
-
J.-J. Liou, L.-C. Wang, A. Krstic, and K.-T. Cheng, "Experience in Critical Path Selection for Deep Submicron Delay Test and Timing Validation," Proc. ASP-DAC 2003, 751-756.
-
(2003)
Proc. ASP-DAC
, pp. 751-756
-
-
Liou, J.-J.1
Wang, L.-C.2
Krstic, A.3
Cheng, K.-T.4
-
5
-
-
0036443068
-
Finding a Small Set of Longest Testable Paths that Cover Every Gate
-
M. Sharma and J.H. Patel, "Finding a Small Set of Longest Testable Paths that Cover Every Gate," Proc. ITC 2002, pp. 974-982.
-
(2002)
Proc. ITC
, pp. 974-982
-
-
Sharma, M.1
Patel, J.H.2
-
6
-
-
0029718601
-
Segment Delay Faults: A New fault Model
-
K. Heragu, J.H. Patel, and V.D. Agrawal, "Segment Delay Faults: A New fault Model," Proc. VTS 1996, pp. 32-39.
-
(1996)
Proc. VTS
, pp. 32-39
-
-
Heragu, K.1
Patel, J.H.2
Agrawal, V.D.3
-
7
-
-
18144399342
-
ALAPTF: A New Transition Fault Model and the ATPG Algorithm
-
P. Gupta and M.S. Hsiao, "ALAPTF: A New Transition Fault Model and the ATPG Algorithm," Proc. ITC 2004, pp. 1053-1060.
-
(2004)
Proc. ITC
, pp. 1053-1060
-
-
Gupta, P.1
Hsiao, M.S.2
-
8
-
-
33751104057
-
Delay Testing for Nanometer Chips
-
Aug./Sept
-
C. Barnhart, "Delay Testing for Nanometer Chips," Chip Design, Aug./Sept. 2004.
-
(2004)
Chip Design
-
-
Barnhart, C.1
-
9
-
-
0024610924
-
A Statistical Model for Delay-Fault Testing
-
Feb
-
E.S. Park, B. Underwood, T.W. Williams, and M.R. Mercer, "A Statistical Model for Delay-Fault Testing," IEEE Design & Test of Computers, Vol. 6, Issue 1, Feb. 1989.
-
(1989)
IEEE Design & Test of Computers
, vol.6
, Issue.1
-
-
Park, E.S.1
Underwood, B.2
Williams, T.W.3
Mercer, M.R.4
-
10
-
-
33645764914
-
Delay Testing Quality in Timing-Optimized Designs
-
E.S. Park, B. Underwood, T.W. Williams, and M.R. Mercer, "Delay Testing Quality in Timing-Optimized Designs," Proc. ITC 1991, pp. 168-176.
-
(1991)
Proc. ITC
, pp. 168-176
-
-
Park, E.S.1
Underwood, B.2
Williams, T.W.3
Mercer, M.R.4
-
11
-
-
84861443625
-
Evaluation of the Statistical Delay Quality Model
-
Y. Sato, S. Hamada, T. Maeda, A. Takatori, and S. Kajihara, "Evaluation of the Statistical Delay Quality Model," Proc. ASP-DAC 2005, pp.305-310.
-
(2005)
Proc. ASP-DAC
, pp. 305-310
-
-
Sato, Y.1
Hamada, S.2
Maeda, T.3
Takatori, A.4
Kajihara, S.5
-
12
-
-
33847156284
-
Invisible Delay Quality - SDQM Model Lights Up What Could Not Be Seen
-
Y. Sato, S. Hamada, T. Maeda, A. Takatori, and S. Kajihara, "Invisible Delay Quality - SDQM Model Lights Up What Could Not Be Seen," Proc. ITC 2005, pp. 1202-1210.
-
(2005)
Proc. ITC
, pp. 1202-1210
-
-
Sato, Y.1
Hamada, S.2
Maeda, T.3
Takatori, A.4
Kajihara, S.5
-
13
-
-
0032664182
-
On N-detection Test Sets and Variable N-detection Test Sets for Transition Faults
-
I. Pomeranz and S.M. Reddy, "On N-detection Test Sets and Variable N-detection Test Sets for Transition Faults," Proc. VTS I999, pp. 173-180.
-
Proc. VTS I999
, pp. 173-180
-
-
Pomeranz, I.1
Reddy, S.M.2
-
14
-
-
0023567773
-
Efficient Test Coverage Determination for Delay Faults
-
J.L. Carter, V.S. Iyengar, and B.K. Rosen, "Efficient Test Coverage Determination for Delay Faults," Proc. ITC 1987, pp. 418-427.
-
(1987)
Proc. ITC
, pp. 418-427
-
-
Carter, J.L.1
Iyengar, V.S.2
Rosen, B.K.3
-
15
-
-
0024124696
-
Delay Test Generation I - Concepts and Coverage Metrics
-
V.S. Iyengar, B.K. Rosen, and I. Spillinger, "Delay Test Generation I - Concepts and Coverage Metrics," Proc. ITC 1988, pp. 857-866.
-
(1988)
Proc. ITC
, pp. 857-866
-
-
Iyengar, V.S.1
Rosen, B.K.2
Spillinger, I.3
-
16
-
-
0024125809
-
Delay Test Generation II - Concepts and Coverage Metrics
-
V.S. Iyengar, B.K. Rosen, and I. Spillinger, "Delay Test Generation II - Concepts and Coverage Metrics," Proc. ITC 1988, pp. 867-876.
-
(1988)
Proc. ITC
, pp. 867-876
-
-
Iyengar, V.S.1
Rosen, B.K.2
Spillinger, I.3
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