Built-in constraint resolution

Proceedings - International Test Conference

Volumn 2005, Issue , 2005, Pages 697-706

  Giles, Grady ^a   Irby, Joel ^a   Toneva, Daniela ^a   Tsai, Kun Han ^b  

^a ADVANCED MICRO DEVICES   (United States)

^b MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUSBARS; CONSTRAINT THEORY;

CONSTRAINT RESOLUTION; SCAN CIRCUIT CONSTRUCTION;

ELECTRONIC EQUIPMENT MANUFACTURE;

EID: 33847131368     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2005.1584032     Document Type: Conference Paper

References (13)

1. S. Pateras; M.S. Schmookler, "Avoiding unknown states when scanning mutually exclusive latches", International Test Conference, 1995. Pages 311 - 318
2. Kuppuswamy, R.; DesRosier, P.; Feltham, D.; Sheikh, R.; Thadikaran, P. "Full Hold-Scan Systems in Microprocessors: Cost/Benefit Analysis." Intel Technology Journal. http://developer.intel.com/technology/itj/2004/ volume08issue01/ (February 2004).
3. C. Pyron; M. Alexander; J. Golab; G. Joos; B. Long;, R. Molyneaux; R. Raina; N. Tendolkar; "DFT Advances in Motorola's MPC7400, a PowerPC TM Microprocessor", International Test Conference, 1999. Pages 137-146
4. R. Raina, R. Bailey, D. Belete, V. Khosa, R. Molyneaux, J. Prado, A. Razdan, "DFT Advances in Motorola's Next-Generation 74xx PowerPC Microprocessor", International Test Conference, 2000. Pages 131-140
5. T. Kant, "Special Issues with Generation of Contention-Free Vectors in Transition Test", http://www.mugweb.org/members/conferences/2004/ papers/kant_sun.pdf
6. P. Goel and B.C. Rosales, "Test Generation and Dynamic Compaction of Tests," Digest of Papers 1979 Test Conf., pp. 189-192, 1979.
7. J.Waicukauski and E. Lindbloom, "Failure Diagnosis of Structured VLSI", IEEE Design & Test of Computers, 1989, pp. 49-60.
8. T. W. Williams and K.P. Parker, "Design for Testability - A Survey," IEEE Trans. on Computers, Vol. C31, No. 1, pp 2-15, January, 1982.
9. Design-for-Test Common Resources Manual, chapter 8, pp.329-370, v8.2004_6, Mentor Graphics, 2004.
10. J. Rajski, J. Tyszer, M. Kassab, N. Mukherjee, R. Thompson, K.-H. Tsai, A. Hertwig, N. Tamarapalli, G. Mrugalski, G Eide, J. Qian; "Embedded Deterministic Test for Low Cost Manufacturing Test", International Test Conference, 2002, pp. 301- 310.
11. U.S. Patent 4,277,699.
12. S. Mitra, L. J. Avra, E. J. McCluskey; "Scan Synthesis for One-Hot Signals", International Test Conference, 1997, pp.414-422
13. S. Das Gupta, R. G. Walther, T. W.Williams, E. B. Eichelberger, "An Enhancement to LSSD and some Applications of LSSD in Reliability, Availability and Serviceability," 11th International Symposium on Fault-Tolerant Computing Proc., 1981, pp. 32-34.