Transition delay fault test pattern generation considering supply voltage noise in a SOC design

Proceedings - Design Automation Conference

Volumn , Issue , 2007, Pages 533-538

  Ahmed, Nisar ^a   Tehranipoor, Mohammad ^a   Jayaram, Vinay ^b  

^a UNIVERSITY OF CONNECTICUT   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

Delay testing; Supply noise; Test generation

Indexed keywords

CIRCUIT OPERATION; DELAY TESTING; PATH DELAYS; SUPPLY VOLTAGE NOISE;

AUTOMATIC TEST PATTERN GENERATION; CHIP SCALE PACKAGES; SPURIOUS SIGNAL NOISE; TRANSIENT ANALYSIS;

INTEGRATED CIRCUIT TESTING;

EID: 34547339881     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2007.375222     Document Type: Conference Paper

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